mediaop.isa (12236:126ac9da6050) mediaop.isa (12707:7819f067a128)
1// Copyright (c) 2009 The Regents of The University of Michigan
2// Copyright (c) 2015 Advanced Micro Devices, Inc.
3//
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

--- 140 unchanged lines hidden (view full) ---

149 if matcher.search(code):
150 base += "Imm"
151 templates = immTemplates
152 else:
153 base += "Reg"
154 templates = regTemplates
155
156 # Get everything ready for the substitution
1// Copyright (c) 2009 The Regents of The University of Michigan
2// Copyright (c) 2015 Advanced Micro Devices, Inc.
3//
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

--- 140 unchanged lines hidden (view full) ---

149 if matcher.search(code):
150 base += "Imm"
151 templates = immTemplates
152 else:
153 base += "Reg"
154 templates = regTemplates
155
156 # Get everything ready for the substitution
157 iop = InstObjParams(name, Name + suffix, base, {"code" : code})
157 opt_args = []
158 if self.op_class:
159 opt_args.append(self.op_class)
160 iop = InstObjParams(name, Name + suffix, base, {"code" : code},
161 opt_args)
158
159 # Generate the actual code (finally!)
160 header_output += templates[0].subst(iop)
161 decoder_output += templates[1].subst(iop)
162 exec_output += templates[2].subst(iop)
163
164
165 def __new__(mcls, Name, bases, dict):
166 abstract = False
167 name = Name.lower()
168 if "abstract" in dict:
169 abstract = dict['abstract']
170 del dict['abstract']
162
163 # Generate the actual code (finally!)
164 header_output += templates[0].subst(iop)
165 decoder_output += templates[1].subst(iop)
166 exec_output += templates[2].subst(iop)
167
168
169 def __new__(mcls, Name, bases, dict):
170 abstract = False
171 name = Name.lower()
172 if "abstract" in dict:
173 abstract = dict['abstract']
174 del dict['abstract']
175 if not "op_class" in dict:
176 dict["op_class"] = None
171
172 cls = super(MediaOpMeta, mcls).__new__(mcls, Name, bases, dict)
173 if not abstract:
174 cls.className = Name
175 cls.base_mnemonic = name
176 code = cls.code
177
178 # Set up the C++ classes

--- 53 unchanged lines hidden (view full) ---

232 "ext" : self.ext}
233 return allocator
234
235 class Mov2int(MediaOp):
236 def __init__(self, dest, src1, src2 = 0, \
237 size = None, destSize = None, srcSize = None, ext = None):
238 super(Mov2int, self).__init__(dest, src1,\
239 src2, size, destSize, srcSize, ext)
177
178 cls = super(MediaOpMeta, mcls).__new__(mcls, Name, bases, dict)
179 if not abstract:
180 cls.className = Name
181 cls.base_mnemonic = name
182 code = cls.code
183
184 # Set up the C++ classes

--- 53 unchanged lines hidden (view full) ---

238 "ext" : self.ext}
239 return allocator
240
241 class Mov2int(MediaOp):
242 def __init__(self, dest, src1, src2 = 0, \
243 size = None, destSize = None, srcSize = None, ext = None):
244 super(Mov2int, self).__init__(dest, src1,\
245 src2, size, destSize, srcSize, ext)
246 op_class = 'SimdMiscOp'
240 code = '''
241 int items = sizeof(FloatRegBits) / srcSize;
242 int offset = imm8;
243 if (bits(src1, 0) && (ext & 0x1))
244 offset -= items;
245 if (offset >= 0 && offset < items) {
246 uint64_t fpSrcReg1 =
247 bits(FpSrcReg1_uqw,

--- 5 unchanged lines hidden (view full) ---

253 }
254 '''
255
256 class Mov2fp(MediaOp):
257 def __init__(self, dest, src1, src2 = 0, \
258 size = None, destSize = None, srcSize = None, ext = None):
259 super(Mov2fp, self).__init__(dest, src1,\
260 src2, size, destSize, srcSize, ext)
247 code = '''
248 int items = sizeof(FloatRegBits) / srcSize;
249 int offset = imm8;
250 if (bits(src1, 0) && (ext & 0x1))
251 offset -= items;
252 if (offset >= 0 && offset < items) {
253 uint64_t fpSrcReg1 =
254 bits(FpSrcReg1_uqw,

--- 5 unchanged lines hidden (view full) ---

260 }
261 '''
262
263 class Mov2fp(MediaOp):
264 def __init__(self, dest, src1, src2 = 0, \
265 size = None, destSize = None, srcSize = None, ext = None):
266 super(Mov2fp, self).__init__(dest, src1,\
267 src2, size, destSize, srcSize, ext)
268 op_class = 'SimdMiscOp'
261 code = '''
262 int items = sizeof(FloatRegBits) / destSize;
263 int offset = imm8;
264 if (bits(dest, 0) && (ext & 0x1))
265 offset -= items;
266 if (offset >= 0 && offset < items) {
267 uint64_t srcReg1 = pick(SrcReg1, 0, srcSize);
268 FpDestReg_uqw =

--- 5 unchanged lines hidden (view full) ---

274 }
275 '''
276
277 class Movsign(MediaOp):
278 def __init__(self, dest, src, \
279 size = None, destSize = None, srcSize = None, ext = None):
280 super(Movsign, self).__init__(dest, src,\
281 "InstRegIndex(0)", size, destSize, srcSize, ext)
269 code = '''
270 int items = sizeof(FloatRegBits) / destSize;
271 int offset = imm8;
272 if (bits(dest, 0) && (ext & 0x1))
273 offset -= items;
274 if (offset >= 0 && offset < items) {
275 uint64_t srcReg1 = pick(SrcReg1, 0, srcSize);
276 FpDestReg_uqw =

--- 5 unchanged lines hidden (view full) ---

282 }
283 '''
284
285 class Movsign(MediaOp):
286 def __init__(self, dest, src, \
287 size = None, destSize = None, srcSize = None, ext = None):
288 super(Movsign, self).__init__(dest, src,\
289 "InstRegIndex(0)", size, destSize, srcSize, ext)
290 op_class = 'SimdMiscOp'
282 code = '''
283 int items = sizeof(FloatRegBits) / srcSize;
284 uint64_t result = 0;
285 int offset = (ext & 0x1) ? items : 0;
286 for (int i = 0; i < items; i++) {
287 uint64_t picked =
288 bits(FpSrcReg1_uqw, (i + 1) * 8 * srcSize - 1);
289 result = insertBits(result, i + offset, i + offset, picked);
290 }
291 DestReg = DestReg | result;
292 '''
293
294 class Maskmov(MediaOp):
291 code = '''
292 int items = sizeof(FloatRegBits) / srcSize;
293 uint64_t result = 0;
294 int offset = (ext & 0x1) ? items : 0;
295 for (int i = 0; i < items; i++) {
296 uint64_t picked =
297 bits(FpSrcReg1_uqw, (i + 1) * 8 * srcSize - 1);
298 result = insertBits(result, i + offset, i + offset, picked);
299 }
300 DestReg = DestReg | result;
301 '''
302
303 class Maskmov(MediaOp):
304 op_class = 'SimdMiscOp'
295 code = '''
296 assert(srcSize == destSize);
297 int size = srcSize;
298 int sizeBits = size * 8;
299 int items = numItems(size);
300 uint64_t result = FpDestReg_uqw;
301
302 for (int i = 0; i < items; i++) {
303 int hiIndex = (i + 1) * sizeBits - 1;
304 int loIndex = (i + 0) * sizeBits;
305 uint64_t arg1Bits = bits(FpSrcReg1_uqw, hiIndex, loIndex);
306 if (bits(FpSrcReg2_uqw, hiIndex))
307 result = insertBits(result, hiIndex, loIndex, arg1Bits);
308 }
309 FpDestReg_uqw = result;
310 '''
311
312 class shuffle(MediaOp):
305 code = '''
306 assert(srcSize == destSize);
307 int size = srcSize;
308 int sizeBits = size * 8;
309 int items = numItems(size);
310 uint64_t result = FpDestReg_uqw;
311
312 for (int i = 0; i < items; i++) {
313 int hiIndex = (i + 1) * sizeBits - 1;
314 int loIndex = (i + 0) * sizeBits;
315 uint64_t arg1Bits = bits(FpSrcReg1_uqw, hiIndex, loIndex);
316 if (bits(FpSrcReg2_uqw, hiIndex))
317 result = insertBits(result, hiIndex, loIndex, arg1Bits);
318 }
319 FpDestReg_uqw = result;
320 '''
321
322 class shuffle(MediaOp):
323 op_class = 'SimdMiscOp'
313 code = '''
314 assert(srcSize == destSize);
315 int size = srcSize;
316 int sizeBits = size * 8;
317 int items = sizeof(FloatRegBits) / size;
318 int options;
319 int optionBits;
320 if (size == 8) {

--- 26 unchanged lines hidden (view full) ---

347 int hiIndex = (i + 1) * sizeBits - 1;
348 int loIndex = (i + 0) * sizeBits;
349 result = insertBits(result, hiIndex, loIndex, resBits);
350 }
351 FpDestReg_uqw = result;
352 '''
353
354 class Unpack(MediaOp):
324 code = '''
325 assert(srcSize == destSize);
326 int size = srcSize;
327 int sizeBits = size * 8;
328 int items = sizeof(FloatRegBits) / size;
329 int options;
330 int optionBits;
331 if (size == 8) {

--- 26 unchanged lines hidden (view full) ---

358 int hiIndex = (i + 1) * sizeBits - 1;
359 int loIndex = (i + 0) * sizeBits;
360 result = insertBits(result, hiIndex, loIndex, resBits);
361 }
362 FpDestReg_uqw = result;
363 '''
364
365 class Unpack(MediaOp):
366 op_class = 'SimdMiscOp'
355 code = '''
356 assert(srcSize == destSize);
357 int size = destSize;
358 int items = (sizeof(FloatRegBits) / size) / 2;
359 int offset = ext ? items : 0;
360 uint64_t result = 0;
361 for (int i = 0; i < items; i++) {
362 uint64_t pickedLow =

--- 10 unchanged lines hidden (view full) ---

373 (2 * i + 2) * 8 * size - 1,
374 (2 * i + 1) * 8 * size,
375 pickedHigh);
376 }
377 FpDestReg_uqw = result;
378 '''
379
380 class Pack(MediaOp):
367 code = '''
368 assert(srcSize == destSize);
369 int size = destSize;
370 int items = (sizeof(FloatRegBits) / size) / 2;
371 int offset = ext ? items : 0;
372 uint64_t result = 0;
373 for (int i = 0; i < items; i++) {
374 uint64_t pickedLow =

--- 10 unchanged lines hidden (view full) ---

385 (2 * i + 2) * 8 * size - 1,
386 (2 * i + 1) * 8 * size,
387 pickedHigh);
388 }
389 FpDestReg_uqw = result;
390 '''
391
392 class Pack(MediaOp):
393 op_class = 'SimdMiscOp'
381 code = '''
382 assert(srcSize == destSize * 2);
383 int items = (sizeof(FloatRegBits) / destSize);
384 int destBits = destSize * 8;
385 int srcBits = srcSize * 8;
386 uint64_t result = 0;
387 int i;
388 for (i = 0; i < items / 2; i++) {

--- 53 unchanged lines hidden (view full) ---

442 picked);
443 }
444 FpDestReg_uqw = result;
445 '''
446
447 class Mxor(MediaOp):
448 def __init__(self, dest, src1, src2):
449 super(Mxor, self).__init__(dest, src1, src2, 1)
394 code = '''
395 assert(srcSize == destSize * 2);
396 int items = (sizeof(FloatRegBits) / destSize);
397 int destBits = destSize * 8;
398 int srcBits = srcSize * 8;
399 uint64_t result = 0;
400 int i;
401 for (i = 0; i < items / 2; i++) {

--- 53 unchanged lines hidden (view full) ---

455 picked);
456 }
457 FpDestReg_uqw = result;
458 '''
459
460 class Mxor(MediaOp):
461 def __init__(self, dest, src1, src2):
462 super(Mxor, self).__init__(dest, src1, src2, 1)
463 op_class = 'SimdAluOp'
450 code = '''
451 FpDestReg_uqw = FpSrcReg1_uqw ^ FpSrcReg2_uqw;
452 '''
453
454 class Mor(MediaOp):
455 def __init__(self, dest, src1, src2):
456 super(Mor, self).__init__(dest, src1, src2, 1)
464 code = '''
465 FpDestReg_uqw = FpSrcReg1_uqw ^ FpSrcReg2_uqw;
466 '''
467
468 class Mor(MediaOp):
469 def __init__(self, dest, src1, src2):
470 super(Mor, self).__init__(dest, src1, src2, 1)
471 op_class = 'SimdAluOp'
457 code = '''
458 FpDestReg_uqw = FpSrcReg1_uqw | FpSrcReg2_uqw;
459 '''
460
461 class Mand(MediaOp):
462 def __init__(self, dest, src1, src2):
463 super(Mand, self).__init__(dest, src1, src2, 1)
472 code = '''
473 FpDestReg_uqw = FpSrcReg1_uqw | FpSrcReg2_uqw;
474 '''
475
476 class Mand(MediaOp):
477 def __init__(self, dest, src1, src2):
478 super(Mand, self).__init__(dest, src1, src2, 1)
479 op_class = 'SimdAluOp'
464 code = '''
465 FpDestReg_uqw = FpSrcReg1_uqw & FpSrcReg2_uqw;
466 '''
467
468 class Mandn(MediaOp):
469 def __init__(self, dest, src1, src2):
470 super(Mandn, self).__init__(dest, src1, src2, 1)
480 code = '''
481 FpDestReg_uqw = FpSrcReg1_uqw & FpSrcReg2_uqw;
482 '''
483
484 class Mandn(MediaOp):
485 def __init__(self, dest, src1, src2):
486 super(Mandn, self).__init__(dest, src1, src2, 1)
487 op_class = 'SimdAluOp'
471 code = '''
472 FpDestReg_uqw = ~FpSrcReg1_uqw & FpSrcReg2_uqw;
473 '''
474
475 class Mminf(MediaOp):
488 code = '''
489 FpDestReg_uqw = ~FpSrcReg1_uqw & FpSrcReg2_uqw;
490 '''
491
492 class Mminf(MediaOp):
493 op_class = 'SimdFloatCmpOp'
476 code = '''
477 union floatInt
478 {
479 float f;
480 uint32_t i;
481 };
482 union doubleInt
483 {

--- 34 unchanged lines hidden (view full) ---

518 } else {
519 result = insertBits(result, hiIndex, loIndex, arg2Bits);
520 }
521 }
522 FpDestReg_uqw = result;
523 '''
524
525 class Mmaxf(MediaOp):
494 code = '''
495 union floatInt
496 {
497 float f;
498 uint32_t i;
499 };
500 union doubleInt
501 {

--- 34 unchanged lines hidden (view full) ---

536 } else {
537 result = insertBits(result, hiIndex, loIndex, arg2Bits);
538 }
539 }
540 FpDestReg_uqw = result;
541 '''
542
543 class Mmaxf(MediaOp):
544 op_class = 'SimdFloatCmpOp'
526 code = '''
527 union floatInt
528 {
529 float f;
530 uint32_t i;
531 };
532 union doubleInt
533 {

--- 34 unchanged lines hidden (view full) ---

568 } else {
569 result = insertBits(result, hiIndex, loIndex, arg2Bits);
570 }
571 }
572 FpDestReg_uqw = result;
573 '''
574
575 class Mmini(MediaOp):
545 code = '''
546 union floatInt
547 {
548 float f;
549 uint32_t i;
550 };
551 union doubleInt
552 {

--- 34 unchanged lines hidden (view full) ---

587 } else {
588 result = insertBits(result, hiIndex, loIndex, arg2Bits);
589 }
590 }
591 FpDestReg_uqw = result;
592 '''
593
594 class Mmini(MediaOp):
595 op_class = 'SimdCmpOp'
576 code = '''
577
578 assert(srcSize == destSize);
579 int size = srcSize;
580 int sizeBits = size * 8;
581 int items = numItems(size);
582 uint64_t result = FpDestReg_uqw;
583

--- 22 unchanged lines hidden (view full) ---

606 }
607 }
608 result = insertBits(result, hiIndex, loIndex, resBits);
609 }
610 FpDestReg_uqw = result;
611 '''
612
613 class Mmaxi(MediaOp):
596 code = '''
597
598 assert(srcSize == destSize);
599 int size = srcSize;
600 int sizeBits = size * 8;
601 int items = numItems(size);
602 uint64_t result = FpDestReg_uqw;
603

--- 22 unchanged lines hidden (view full) ---

626 }
627 }
628 result = insertBits(result, hiIndex, loIndex, resBits);
629 }
630 FpDestReg_uqw = result;
631 '''
632
633 class Mmaxi(MediaOp):
634 op_class = 'SimdCmpOp'
614 code = '''
615
616 assert(srcSize == destSize);
617 int size = srcSize;
618 int sizeBits = size * 8;
619 int items = numItems(size);
620 uint64_t result = FpDestReg_uqw;
621

--- 22 unchanged lines hidden (view full) ---

644 }
645 }
646 result = insertBits(result, hiIndex, loIndex, resBits);
647 }
648 FpDestReg_uqw = result;
649 '''
650
651 class Msqrt(MediaOp):
635 code = '''
636
637 assert(srcSize == destSize);
638 int size = srcSize;
639 int sizeBits = size * 8;
640 int items = numItems(size);
641 uint64_t result = FpDestReg_uqw;
642

--- 22 unchanged lines hidden (view full) ---

665 }
666 }
667 result = insertBits(result, hiIndex, loIndex, resBits);
668 }
669 FpDestReg_uqw = result;
670 '''
671
672 class Msqrt(MediaOp):
673 op_class = 'SimdFloatSqrtOp'
652 def __init__(self, dest, src, \
653 size = None, destSize = None, srcSize = None, ext = None):
654 super(Msqrt, self).__init__(dest, src,\
655 "InstRegIndex(0)", size, destSize, srcSize, ext)
656 code = '''
657 union floatInt
658 {
659 float f;

--- 34 unchanged lines hidden (view full) ---

694 '''
695
696 # compute approximate reciprocal --- single-precision only
697 class Mrcp(MediaOp):
698 def __init__(self, dest, src, \
699 size = None, destSize = None, srcSize = None, ext = None):
700 super(Mrcp, self).__init__(dest, src,\
701 "InstRegIndex(0)", size, destSize, srcSize, ext)
674 def __init__(self, dest, src, \
675 size = None, destSize = None, srcSize = None, ext = None):
676 super(Msqrt, self).__init__(dest, src,\
677 "InstRegIndex(0)", size, destSize, srcSize, ext)
678 code = '''
679 union floatInt
680 {
681 float f;

--- 34 unchanged lines hidden (view full) ---

716 '''
717
718 # compute approximate reciprocal --- single-precision only
719 class Mrcp(MediaOp):
720 def __init__(self, dest, src, \
721 size = None, destSize = None, srcSize = None, ext = None):
722 super(Mrcp, self).__init__(dest, src,\
723 "InstRegIndex(0)", size, destSize, srcSize, ext)
724 op_class = 'SimdFloatAluOp'
702 code = '''
703 union floatInt
704 {
705 float f;
706 uint32_t i;
707 };
708
709 assert(srcSize == 4); // ISA defines single-precision only

--- 14 unchanged lines hidden (view full) ---

724 fi.f = 1.0 / fi.f;
725 argBits = fi.i;
726 result = insertBits(result, hiIndex, loIndex, argBits);
727 }
728 FpDestReg_uqw = result;
729 '''
730
731 class Maddf(MediaOp):
725 code = '''
726 union floatInt
727 {
728 float f;
729 uint32_t i;
730 };
731
732 assert(srcSize == 4); // ISA defines single-precision only

--- 14 unchanged lines hidden (view full) ---

747 fi.f = 1.0 / fi.f;
748 argBits = fi.i;
749 result = insertBits(result, hiIndex, loIndex, argBits);
750 }
751 FpDestReg_uqw = result;
752 '''
753
754 class Maddf(MediaOp):
755 op_class = 'SimdFloatAddOp'
732 code = '''
733 union floatInt
734 {
735 float f;
736 uint32_t i;
737 };
738 union doubleInt
739 {

--- 30 unchanged lines hidden (view full) ---

770 }
771
772 result = insertBits(result, hiIndex, loIndex, resBits);
773 }
774 FpDestReg_uqw = result;
775 '''
776
777 class Msubf(MediaOp):
756 code = '''
757 union floatInt
758 {
759 float f;
760 uint32_t i;
761 };
762 union doubleInt
763 {

--- 30 unchanged lines hidden (view full) ---

794 }
795
796 result = insertBits(result, hiIndex, loIndex, resBits);
797 }
798 FpDestReg_uqw = result;
799 '''
800
801 class Msubf(MediaOp):
802 op_class = 'SimdFloatAddOp'
778 code = '''
779 union floatInt
780 {
781 float f;
782 uint32_t i;
783 };
784 union doubleInt
785 {

--- 30 unchanged lines hidden (view full) ---

816 }
817
818 result = insertBits(result, hiIndex, loIndex, resBits);
819 }
820 FpDestReg_uqw = result;
821 '''
822
823 class Mmulf(MediaOp):
803 code = '''
804 union floatInt
805 {
806 float f;
807 uint32_t i;
808 };
809 union doubleInt
810 {

--- 30 unchanged lines hidden (view full) ---

841 }
842
843 result = insertBits(result, hiIndex, loIndex, resBits);
844 }
845 FpDestReg_uqw = result;
846 '''
847
848 class Mmulf(MediaOp):
849 op_class = 'SimdFloatMultOp'
824 code = '''
825 union floatInt
826 {
827 float f;
828 uint32_t i;
829 };
830 union doubleInt
831 {

--- 30 unchanged lines hidden (view full) ---

862 }
863
864 result = insertBits(result, hiIndex, loIndex, resBits);
865 }
866 FpDestReg_uqw = result;
867 '''
868
869 class Mdivf(MediaOp):
850 code = '''
851 union floatInt
852 {
853 float f;
854 uint32_t i;
855 };
856 union doubleInt
857 {

--- 30 unchanged lines hidden (view full) ---

888 }
889
890 result = insertBits(result, hiIndex, loIndex, resBits);
891 }
892 FpDestReg_uqw = result;
893 '''
894
895 class Mdivf(MediaOp):
896 op_class = 'SimdFloatDivOp'
870 code = '''
871 union floatInt
872 {
873 float f;
874 uint32_t i;
875 };
876 union doubleInt
877 {

--- 30 unchanged lines hidden (view full) ---

908 }
909
910 result = insertBits(result, hiIndex, loIndex, resBits);
911 }
912 FpDestReg_uqw = result;
913 '''
914
915 class Maddi(MediaOp):
897 code = '''
898 union floatInt
899 {
900 float f;
901 uint32_t i;
902 };
903 union doubleInt
904 {

--- 30 unchanged lines hidden (view full) ---

935 }
936
937 result = insertBits(result, hiIndex, loIndex, resBits);
938 }
939 FpDestReg_uqw = result;
940 '''
941
942 class Maddi(MediaOp):
943 op_class = 'SimdAddOp'
916 code = '''
917 assert(srcSize == destSize);
918 int size = srcSize;
919 int sizeBits = size * 8;
920 int items = numItems(size);
921 uint64_t result = FpDestReg_uqw;
922
923 for (int i = 0; i < items; i++) {

--- 21 unchanged lines hidden (view full) ---

945 }
946
947 result = insertBits(result, hiIndex, loIndex, resBits);
948 }
949 FpDestReg_uqw = result;
950 '''
951
952 class Msubi(MediaOp):
944 code = '''
945 assert(srcSize == destSize);
946 int size = srcSize;
947 int sizeBits = size * 8;
948 int items = numItems(size);
949 uint64_t result = FpDestReg_uqw;
950
951 for (int i = 0; i < items; i++) {

--- 21 unchanged lines hidden (view full) ---

973 }
974
975 result = insertBits(result, hiIndex, loIndex, resBits);
976 }
977 FpDestReg_uqw = result;
978 '''
979
980 class Msubi(MediaOp):
981 op_class = 'SimdAddOp'
953 code = '''
954 assert(srcSize == destSize);
955 int size = srcSize;
956 int sizeBits = size * 8;
957 int items = numItems(size);
958 uint64_t result = FpDestReg_uqw;
959
960 for (int i = 0; i < items; i++) {

--- 25 unchanged lines hidden (view full) ---

986 }
987
988 result = insertBits(result, hiIndex, loIndex, resBits);
989 }
990 FpDestReg_uqw = result;
991 '''
992
993 class Mmuli(MediaOp):
982 code = '''
983 assert(srcSize == destSize);
984 int size = srcSize;
985 int sizeBits = size * 8;
986 int items = numItems(size);
987 uint64_t result = FpDestReg_uqw;
988
989 for (int i = 0; i < items; i++) {

--- 25 unchanged lines hidden (view full) ---

1015 }
1016
1017 result = insertBits(result, hiIndex, loIndex, resBits);
1018 }
1019 FpDestReg_uqw = result;
1020 '''
1021
1022 class Mmuli(MediaOp):
1023 op_class = 'SimdMultOp'
994 code = '''
995 int srcBits = srcSize * 8;
996 int destBits = destSize * 8;
997 assert(destBits <= 64);
998 assert(destSize >= srcSize);
999 int items = numItems(destSize);
1000 uint64_t result = FpDestReg_uqw;
1001

--- 30 unchanged lines hidden (view full) ---

1032 int destHiIndex = (i + 1) * destBits - 1;
1033 int destLoIndex = (i + 0) * destBits;
1034 result = insertBits(result, destHiIndex, destLoIndex, resBits);
1035 }
1036 FpDestReg_uqw = result;
1037 '''
1038
1039 class Mavg(MediaOp):
1024 code = '''
1025 int srcBits = srcSize * 8;
1026 int destBits = destSize * 8;
1027 assert(destBits <= 64);
1028 assert(destSize >= srcSize);
1029 int items = numItems(destSize);
1030 uint64_t result = FpDestReg_uqw;
1031

--- 30 unchanged lines hidden (view full) ---

1062 int destHiIndex = (i + 1) * destBits - 1;
1063 int destLoIndex = (i + 0) * destBits;
1064 result = insertBits(result, destHiIndex, destLoIndex, resBits);
1065 }
1066 FpDestReg_uqw = result;
1067 '''
1068
1069 class Mavg(MediaOp):
1070 op_class = 'SimdAddOp'
1040 code = '''
1041 assert(srcSize == destSize);
1042 int size = srcSize;
1043 int sizeBits = size * 8;
1044 int items = numItems(size);
1045 uint64_t result = FpDestReg_uqw;
1046
1047 for (int i = 0; i < items; i++) {

--- 4 unchanged lines hidden (view full) ---

1052 uint64_t resBits = (arg1Bits + arg2Bits + 1) / 2;
1053
1054 result = insertBits(result, hiIndex, loIndex, resBits);
1055 }
1056 FpDestReg_uqw = result;
1057 '''
1058
1059 class Msad(MediaOp):
1071 code = '''
1072 assert(srcSize == destSize);
1073 int size = srcSize;
1074 int sizeBits = size * 8;
1075 int items = numItems(size);
1076 uint64_t result = FpDestReg_uqw;
1077
1078 for (int i = 0; i < items; i++) {

--- 4 unchanged lines hidden (view full) ---

1083 uint64_t resBits = (arg1Bits + arg2Bits + 1) / 2;
1084
1085 result = insertBits(result, hiIndex, loIndex, resBits);
1086 }
1087 FpDestReg_uqw = result;
1088 '''
1089
1090 class Msad(MediaOp):
1091 op_class = 'SimdAddOp'
1060 code = '''
1061 int srcBits = srcSize * 8;
1062 int items = sizeof(FloatRegBits) / srcSize;
1063
1064 uint64_t sum = 0;
1065 for (int i = 0; i < items; i++) {
1066 int hiIndex = (i + 1) * srcBits - 1;
1067 int loIndex = (i + 0) * srcBits;
1068 uint64_t arg1Bits = bits(FpSrcReg1_uqw, hiIndex, loIndex);
1069 uint64_t arg2Bits = bits(FpSrcReg2_uqw, hiIndex, loIndex);
1070 int64_t resBits = arg1Bits - arg2Bits;
1071 if (resBits < 0)
1072 resBits = -resBits;
1073 sum += resBits;
1074 }
1075 FpDestReg_uqw = sum & mask(destSize * 8);
1076 '''
1077
1078 class Msrl(MediaOp):
1092 code = '''
1093 int srcBits = srcSize * 8;
1094 int items = sizeof(FloatRegBits) / srcSize;
1095
1096 uint64_t sum = 0;
1097 for (int i = 0; i < items; i++) {
1098 int hiIndex = (i + 1) * srcBits - 1;
1099 int loIndex = (i + 0) * srcBits;
1100 uint64_t arg1Bits = bits(FpSrcReg1_uqw, hiIndex, loIndex);
1101 uint64_t arg2Bits = bits(FpSrcReg2_uqw, hiIndex, loIndex);
1102 int64_t resBits = arg1Bits - arg2Bits;
1103 if (resBits < 0)
1104 resBits = -resBits;
1105 sum += resBits;
1106 }
1107 FpDestReg_uqw = sum & mask(destSize * 8);
1108 '''
1109
1110 class Msrl(MediaOp):
1111 op_class = 'SimdShiftOp'
1079 code = '''
1080
1081 assert(srcSize == destSize);
1082 int size = srcSize;
1083 int sizeBits = size * 8;
1084 int items = numItems(size);
1085 uint64_t shiftAmt = op2_uqw;
1086 uint64_t result = FpDestReg_uqw;

--- 11 unchanged lines hidden (view full) ---

1098 }
1099
1100 result = insertBits(result, hiIndex, loIndex, resBits);
1101 }
1102 FpDestReg_uqw = result;
1103 '''
1104
1105 class Msra(MediaOp):
1112 code = '''
1113
1114 assert(srcSize == destSize);
1115 int size = srcSize;
1116 int sizeBits = size * 8;
1117 int items = numItems(size);
1118 uint64_t shiftAmt = op2_uqw;
1119 uint64_t result = FpDestReg_uqw;

--- 11 unchanged lines hidden (view full) ---

1131 }
1132
1133 result = insertBits(result, hiIndex, loIndex, resBits);
1134 }
1135 FpDestReg_uqw = result;
1136 '''
1137
1138 class Msra(MediaOp):
1139 op_class = 'SimdShiftOp'
1106 code = '''
1107
1108 assert(srcSize == destSize);
1109 int size = srcSize;
1110 int sizeBits = size * 8;
1111 int items = numItems(size);
1112 uint64_t shiftAmt = op2_uqw;
1113 uint64_t result = FpDestReg_uqw;

--- 15 unchanged lines hidden (view full) ---

1129 }
1130
1131 result = insertBits(result, hiIndex, loIndex, resBits);
1132 }
1133 FpDestReg_uqw = result;
1134 '''
1135
1136 class Msll(MediaOp):
1140 code = '''
1141
1142 assert(srcSize == destSize);
1143 int size = srcSize;
1144 int sizeBits = size * 8;
1145 int items = numItems(size);
1146 uint64_t shiftAmt = op2_uqw;
1147 uint64_t result = FpDestReg_uqw;

--- 15 unchanged lines hidden (view full) ---

1163 }
1164
1165 result = insertBits(result, hiIndex, loIndex, resBits);
1166 }
1167 FpDestReg_uqw = result;
1168 '''
1169
1170 class Msll(MediaOp):
1171 op_class = 'SimdShiftOp'
1137 code = '''
1138
1139 assert(srcSize == destSize);
1140 int size = srcSize;
1141 int sizeBits = size * 8;
1142 int items = numItems(size);
1143 uint64_t shiftAmt = op2_uqw;
1144 uint64_t result = FpDestReg_uqw;

--- 14 unchanged lines hidden (view full) ---

1159 FpDestReg_uqw = result;
1160 '''
1161
1162 class Cvtf2i(MediaOp):
1163 def __init__(self, dest, src, \
1164 size = None, destSize = None, srcSize = None, ext = None):
1165 super(Cvtf2i, self).__init__(dest, src,\
1166 "InstRegIndex(0)", size, destSize, srcSize, ext)
1172 code = '''
1173
1174 assert(srcSize == destSize);
1175 int size = srcSize;
1176 int sizeBits = size * 8;
1177 int items = numItems(size);
1178 uint64_t shiftAmt = op2_uqw;
1179 uint64_t result = FpDestReg_uqw;

--- 14 unchanged lines hidden (view full) ---

1194 FpDestReg_uqw = result;
1195 '''
1196
1197 class Cvtf2i(MediaOp):
1198 def __init__(self, dest, src, \
1199 size = None, destSize = None, srcSize = None, ext = None):
1200 super(Cvtf2i, self).__init__(dest, src,\
1201 "InstRegIndex(0)", size, destSize, srcSize, ext)
1202 op_class = 'SimdFloatCvtOp'
1167 code = '''
1168 union floatInt
1169 {
1170 float f;
1171 uint32_t i;
1172 };
1173 union doubleInt
1174 {

--- 58 unchanged lines hidden (view full) ---

1233 FpDestReg_uqw = result;
1234 '''
1235
1236 class Cvti2f(MediaOp):
1237 def __init__(self, dest, src, \
1238 size = None, destSize = None, srcSize = None, ext = None):
1239 super(Cvti2f, self).__init__(dest, src,\
1240 "InstRegIndex(0)", size, destSize, srcSize, ext)
1203 code = '''
1204 union floatInt
1205 {
1206 float f;
1207 uint32_t i;
1208 };
1209 union doubleInt
1210 {

--- 58 unchanged lines hidden (view full) ---

1269 FpDestReg_uqw = result;
1270 '''
1271
1272 class Cvti2f(MediaOp):
1273 def __init__(self, dest, src, \
1274 size = None, destSize = None, srcSize = None, ext = None):
1275 super(Cvti2f, self).__init__(dest, src,\
1276 "InstRegIndex(0)", size, destSize, srcSize, ext)
1277 op_class = 'SimdFloatCvtOp'
1241 code = '''
1242 union floatInt
1243 {
1244 float f;
1245 uint32_t i;
1246 };
1247 union doubleInt
1248 {

--- 46 unchanged lines hidden (view full) ---

1295 FpDestReg_uqw = result;
1296 '''
1297
1298 class Cvtf2f(MediaOp):
1299 def __init__(self, dest, src, \
1300 size = None, destSize = None, srcSize = None, ext = None):
1301 super(Cvtf2f, self).__init__(dest, src,\
1302 "InstRegIndex(0)", size, destSize, srcSize, ext)
1278 code = '''
1279 union floatInt
1280 {
1281 float f;
1282 uint32_t i;
1283 };
1284 union doubleInt
1285 {

--- 46 unchanged lines hidden (view full) ---

1332 FpDestReg_uqw = result;
1333 '''
1334
1335 class Cvtf2f(MediaOp):
1336 def __init__(self, dest, src, \
1337 size = None, destSize = None, srcSize = None, ext = None):
1338 super(Cvtf2f, self).__init__(dest, src,\
1339 "InstRegIndex(0)", size, destSize, srcSize, ext)
1340 op_class = 'SimdFloatCvtOp'
1303 code = '''
1304 union floatInt
1305 {
1306 float f;
1307 uint32_t i;
1308 };
1309 union doubleInt
1310 {

--- 48 unchanged lines hidden (view full) ---

1359 int destHiIndex = destStart + (i + 1) * destSizeBits - 1;
1360 int destLoIndex = destStart + (i + 0) * destSizeBits;
1361 result = insertBits(result, destHiIndex, destLoIndex, argBits);
1362 }
1363 FpDestReg_uqw = result;
1364 '''
1365
1366 class Mcmpi2r(MediaOp):
1341 code = '''
1342 union floatInt
1343 {
1344 float f;
1345 uint32_t i;
1346 };
1347 union doubleInt
1348 {

--- 48 unchanged lines hidden (view full) ---

1397 int destHiIndex = destStart + (i + 1) * destSizeBits - 1;
1398 int destLoIndex = destStart + (i + 0) * destSizeBits;
1399 result = insertBits(result, destHiIndex, destLoIndex, argBits);
1400 }
1401 FpDestReg_uqw = result;
1402 '''
1403
1404 class Mcmpi2r(MediaOp):
1405 op_class = 'SimdCvtOp'
1367 code = '''
1368 union floatInt
1369 {
1370 float f;
1371 uint32_t i;
1372 };
1373 union doubleInt
1374 {

--- 23 unchanged lines hidden (view full) ---

1398 resBits = mask(sizeBits);
1399
1400 result = insertBits(result, hiIndex, loIndex, resBits);
1401 }
1402 FpDestReg_uqw = result;
1403 '''
1404
1405 class Mcmpf2r(MediaOp):
1406 code = '''
1407 union floatInt
1408 {
1409 float f;
1410 uint32_t i;
1411 };
1412 union doubleInt
1413 {

--- 23 unchanged lines hidden (view full) ---

1437 resBits = mask(sizeBits);
1438
1439 result = insertBits(result, hiIndex, loIndex, resBits);
1440 }
1441 FpDestReg_uqw = result;
1442 '''
1443
1444 class Mcmpf2r(MediaOp):
1445 op_class = 'SimdFloatCvtOp'
1406 code = '''
1407 union floatInt
1408 {
1409 float f;
1410 uint32_t i;
1411 };
1412 union doubleInt
1413 {

--- 70 unchanged lines hidden (view full) ---

1484 FpDestReg_uqw = result;
1485 '''
1486
1487 class Mcmpf2rf(MediaOp):
1488 def __init__(self, src1, src2,\
1489 size = None, destSize = None, srcSize = None, ext = None):
1490 super(Mcmpf2rf, self).__init__("InstRegIndex(0)", src1,\
1491 src2, size, destSize, srcSize, ext)
1446 code = '''
1447 union floatInt
1448 {
1449 float f;
1450 uint32_t i;
1451 };
1452 union doubleInt
1453 {

--- 70 unchanged lines hidden (view full) ---

1524 FpDestReg_uqw = result;
1525 '''
1526
1527 class Mcmpf2rf(MediaOp):
1528 def __init__(self, src1, src2,\
1529 size = None, destSize = None, srcSize = None, ext = None):
1530 super(Mcmpf2rf, self).__init__("InstRegIndex(0)", src1,\
1531 src2, size, destSize, srcSize, ext)
1532 op_class = 'SimdFloatCvtOp'
1492 code = '''
1493 union floatInt
1494 {
1495 float f;
1496 uint32_t i;
1497 };
1498 union doubleInt
1499 {

--- 38 unchanged lines hidden (view full) ---

1538 }
1539 else if(arg1 < arg2)
1540 cfofBits = cfofBits | CFBit;
1541 else if(arg1 == arg2)
1542 ccFlagBits = ccFlagBits | ZFBit;
1543 '''
1544
1545 class Emms(MediaOp):
1533 code = '''
1534 union floatInt
1535 {
1536 float f;
1537 uint32_t i;
1538 };
1539 union doubleInt
1540 {

--- 38 unchanged lines hidden (view full) ---

1579 }
1580 else if(arg1 < arg2)
1581 cfofBits = cfofBits | CFBit;
1582 else if(arg1 == arg2)
1583 ccFlagBits = ccFlagBits | ZFBit;
1584 '''
1585
1586 class Emms(MediaOp):
1587 op_class = 'FloatMiscOp'
1546 def __init__(self):
1547 super(Emms, self).__init__('InstRegIndex(MISCREG_FTW)',
1548 'InstRegIndex(0)', 'InstRegIndex(0)', 2)
1549 code = 'FTW = 0xFFFF;'
1550}};
1588 def __init__(self):
1589 super(Emms, self).__init__('InstRegIndex(MISCREG_FTW)',
1590 'InstRegIndex(0)', 'InstRegIndex(0)', 2)
1591 code = 'FTW = 0xFFFF;'
1592}};