ldstop.isa (8102:77ee9ad2e113) | ldstop.isa (8103:53c2d9b1c15d) |
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1// Copyright (c) 2007-2008 The Hewlett-Packard Development Company 2// All rights reserved. 3// 4// The license below extends only to copyright in the software and shall 5// not be construed as granting a license to any other intellectual 6// property including but not limited to intellectual property relating 7// to a hardware implementation of the functionality of the software 8// licensed hereunder. You may use the software subject to the license --- 258 unchanged lines hidden (view full) --- 267 { 268 %(constructor)s; 269 } 270}}; 271 272let {{ 273 class LdStOp(X86Microop): 274 def __init__(self, data, segment, addr, disp, | 1// Copyright (c) 2007-2008 The Hewlett-Packard Development Company 2// All rights reserved. 3// 4// The license below extends only to copyright in the software and shall 5// not be construed as granting a license to any other intellectual 6// property including but not limited to intellectual property relating 7// to a hardware implementation of the functionality of the software 8// licensed hereunder. You may use the software subject to the license --- 258 unchanged lines hidden (view full) --- 267 { 268 %(constructor)s; 269 } 270}}; 271 272let {{ 273 class LdStOp(X86Microop): 274 def __init__(self, data, segment, addr, disp, |
275 dataSize, addressSize, baseFlags, atCPL0, prefetch): | 275 dataSize, addressSize, baseFlags, atCPL0, prefetch, nonSpec): |
276 self.data = data 277 [self.scale, self.index, self.base] = addr 278 self.disp = disp 279 self.segment = segment 280 self.dataSize = dataSize 281 self.addressSize = addressSize 282 self.memFlags = baseFlags 283 if atCPL0: 284 self.memFlags += " | (CPL0FlagBit << FlagShift)" 285 self.instFlags = "" 286 if prefetch: 287 self.memFlags += " | Request::PREFETCH" | 276 self.data = data 277 [self.scale, self.index, self.base] = addr 278 self.disp = disp 279 self.segment = segment 280 self.dataSize = dataSize 281 self.addressSize = addressSize 282 self.memFlags = baseFlags 283 if atCPL0: 284 self.memFlags += " | (CPL0FlagBit << FlagShift)" 285 self.instFlags = "" 286 if prefetch: 287 self.memFlags += " | Request::PREFETCH" |
288 self.instFlags += " | StaticInst::IsDataPrefetch" | 288 self.instFlags += " | (1ULL << StaticInst::IsDataPrefetch)" 289 if nonSpec: 290 self.instFlags += " | (1ULL << StaticInst::IsNonSpeculative)" |
289 self.memFlags += " | (machInst.legacy.addr ? " + \ 290 "(AddrSizeFlagBit << FlagShift) : 0)" 291 292 def getAllocator(self, microFlags): 293 allocator = '''new %(class_name)s(machInst, macrocodeBlock, 294 %(flags)s, %(scale)s, %(index)s, %(base)s, 295 %(disp)s, %(segment)s, %(data)s, 296 %(dataSize)s, %(addressSize)s, %(memFlags)s)''' % { --- 4 unchanged lines hidden (view full) --- 301 "disp" : self.disp, 302 "segment" : self.segment, "data" : self.data, 303 "dataSize" : self.dataSize, "addressSize" : self.addressSize, 304 "memFlags" : self.memFlags} 305 return allocator 306 307 class BigLdStOp(X86Microop): 308 def __init__(self, data, segment, addr, disp, | 291 self.memFlags += " | (machInst.legacy.addr ? " + \ 292 "(AddrSizeFlagBit << FlagShift) : 0)" 293 294 def getAllocator(self, microFlags): 295 allocator = '''new %(class_name)s(machInst, macrocodeBlock, 296 %(flags)s, %(scale)s, %(index)s, %(base)s, 297 %(disp)s, %(segment)s, %(data)s, 298 %(dataSize)s, %(addressSize)s, %(memFlags)s)''' % { --- 4 unchanged lines hidden (view full) --- 303 "disp" : self.disp, 304 "segment" : self.segment, "data" : self.data, 305 "dataSize" : self.dataSize, "addressSize" : self.addressSize, 306 "memFlags" : self.memFlags} 307 return allocator 308 309 class BigLdStOp(X86Microop): 310 def __init__(self, data, segment, addr, disp, |
309 dataSize, addressSize, baseFlags, atCPL0, prefetch): | 311 dataSize, addressSize, baseFlags, atCPL0, prefetch, nonSpec): |
310 self.data = data 311 [self.scale, self.index, self.base] = addr 312 self.disp = disp 313 self.segment = segment 314 self.dataSize = dataSize 315 self.addressSize = addressSize 316 self.memFlags = baseFlags 317 if atCPL0: 318 self.memFlags += " | (CPL0FlagBit << FlagShift)" | 312 self.data = data 313 [self.scale, self.index, self.base] = addr 314 self.disp = disp 315 self.segment = segment 316 self.dataSize = dataSize 317 self.addressSize = addressSize 318 self.memFlags = baseFlags 319 if atCPL0: 320 self.memFlags += " | (CPL0FlagBit << FlagShift)" |
321 self.instFlags = "" |
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319 if prefetch: 320 self.memFlags += " | Request::PREFETCH" | 322 if prefetch: 323 self.memFlags += " | Request::PREFETCH" |
324 self.instFlags += " | (1ULL << StaticInst::IsDataPrefetch)" 325 if nonSpec: 326 self.instFlags += " | (1ULL << StaticInst::IsNonSpeculative)" |
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321 self.memFlags += " | (machInst.legacy.addr ? " + \ 322 "(AddrSizeFlagBit << FlagShift) : 0)" 323 324 def getAllocator(self, microFlags): 325 allocString = ''' 326 (%(dataSize)s >= 4) ? 327 (StaticInstPtr)(new %(class_name)sBig(machInst, 328 macrocodeBlock, %(flags)s, %(scale)s, %(index)s, 329 %(base)s, %(disp)s, %(segment)s, %(data)s, 330 %(dataSize)s, %(addressSize)s, %(memFlags)s)) : 331 (StaticInstPtr)(new %(class_name)s(machInst, 332 macrocodeBlock, %(flags)s, %(scale)s, %(index)s, 333 %(base)s, %(disp)s, %(segment)s, %(data)s, 334 %(dataSize)s, %(addressSize)s, %(memFlags)s)) 335 ''' 336 allocator = allocString % { 337 "class_name" : self.className, | 327 self.memFlags += " | (machInst.legacy.addr ? " + \ 328 "(AddrSizeFlagBit << FlagShift) : 0)" 329 330 def getAllocator(self, microFlags): 331 allocString = ''' 332 (%(dataSize)s >= 4) ? 333 (StaticInstPtr)(new %(class_name)sBig(machInst, 334 macrocodeBlock, %(flags)s, %(scale)s, %(index)s, 335 %(base)s, %(disp)s, %(segment)s, %(data)s, 336 %(dataSize)s, %(addressSize)s, %(memFlags)s)) : 337 (StaticInstPtr)(new %(class_name)s(machInst, 338 macrocodeBlock, %(flags)s, %(scale)s, %(index)s, 339 %(base)s, %(disp)s, %(segment)s, %(data)s, 340 %(dataSize)s, %(addressSize)s, %(memFlags)s)) 341 ''' 342 allocator = allocString % { 343 "class_name" : self.className, |
338 "flags" : self.microFlagsText(microFlags), | 344 "flags" : self.microFlagsText(microFlags) + self.instFlags, |
339 "scale" : self.scale, "index" : self.index, 340 "base" : self.base, 341 "disp" : self.disp, 342 "segment" : self.segment, "data" : self.data, 343 "dataSize" : self.dataSize, "addressSize" : self.addressSize, 344 "memFlags" : self.memFlags} 345 return allocator 346}}; --- 34 unchanged lines hidden (view full) --- 381 382 base = LdStOp 383 if big: 384 base = BigLdStOp 385 class LoadOp(base): 386 def __init__(self, data, segment, addr, disp = 0, 387 dataSize="env.dataSize", 388 addressSize="env.addressSize", | 345 "scale" : self.scale, "index" : self.index, 346 "base" : self.base, 347 "disp" : self.disp, 348 "segment" : self.segment, "data" : self.data, 349 "dataSize" : self.dataSize, "addressSize" : self.addressSize, 350 "memFlags" : self.memFlags} 351 return allocator 352}}; --- 34 unchanged lines hidden (view full) --- 387 388 base = LdStOp 389 if big: 390 base = BigLdStOp 391 class LoadOp(base): 392 def __init__(self, data, segment, addr, disp = 0, 393 dataSize="env.dataSize", 394 addressSize="env.addressSize", |
389 atCPL0=False, prefetch=False): | 395 atCPL0=False, prefetch=False, nonSpec=False): |
390 super(LoadOp, self).__init__(data, segment, addr, 391 disp, dataSize, addressSize, mem_flags, | 396 super(LoadOp, self).__init__(data, segment, addr, 397 disp, dataSize, addressSize, mem_flags, |
392 atCPL0, prefetch) | 398 atCPL0, prefetch, nonSpec) |
393 self.className = Name 394 self.mnemonic = name 395 396 microopClasses[name] = LoadOp 397 398 defineMicroLoadOp('Ld', 'Data = merge(Data, Mem, dataSize);', 399 'Data = Mem & mask(dataSize * 8);') 400 defineMicroLoadOp('Ldst', 'Data = merge(Data, Mem, dataSize);', --- 24 unchanged lines hidden (view full) --- 425 exec_output += MicroStoreExecute.subst(iop) 426 exec_output += MicroStoreInitiateAcc.subst(iop) 427 exec_output += MicroStoreCompleteAcc.subst(iop) 428 429 class StoreOp(LdStOp): 430 def __init__(self, data, segment, addr, disp = 0, 431 dataSize="env.dataSize", 432 addressSize="env.addressSize", | 399 self.className = Name 400 self.mnemonic = name 401 402 microopClasses[name] = LoadOp 403 404 defineMicroLoadOp('Ld', 'Data = merge(Data, Mem, dataSize);', 405 'Data = Mem & mask(dataSize * 8);') 406 defineMicroLoadOp('Ldst', 'Data = merge(Data, Mem, dataSize);', --- 24 unchanged lines hidden (view full) --- 431 exec_output += MicroStoreExecute.subst(iop) 432 exec_output += MicroStoreInitiateAcc.subst(iop) 433 exec_output += MicroStoreCompleteAcc.subst(iop) 434 435 class StoreOp(LdStOp): 436 def __init__(self, data, segment, addr, disp = 0, 437 dataSize="env.dataSize", 438 addressSize="env.addressSize", |
433 atCPL0=False): 434 super(StoreOp, self).__init__(data, segment, addr, 435 disp, dataSize, addressSize, mem_flags, atCPL0, False) | 439 atCPL0=False, nonSpec=False): 440 super(StoreOp, self).__init__(data, segment, addr, disp, 441 dataSize, addressSize, mem_flags, atCPL0, False, 442 nonSpec) |
436 self.className = Name 437 self.mnemonic = name 438 439 microopClasses[name] = StoreOp 440 441 defineMicroStoreOp('St', 'Mem = pick(Data, 2, dataSize);') 442 defineMicroStoreOp('Stul', 'Mem = pick(Data, 2, dataSize);', 443 mem_flags="Request::LOCKED") --- 7 unchanged lines hidden (view full) --- 451 '''}) 452 header_output += MicroLeaDeclare.subst(iop) 453 decoder_output += MicroLdStOpConstructor.subst(iop) 454 exec_output += MicroLeaExecute.subst(iop) 455 456 class LeaOp(LdStOp): 457 def __init__(self, data, segment, addr, disp = 0, 458 dataSize="env.dataSize", addressSize="env.addressSize"): | 443 self.className = Name 444 self.mnemonic = name 445 446 microopClasses[name] = StoreOp 447 448 defineMicroStoreOp('St', 'Mem = pick(Data, 2, dataSize);') 449 defineMicroStoreOp('Stul', 'Mem = pick(Data, 2, dataSize);', 450 mem_flags="Request::LOCKED") --- 7 unchanged lines hidden (view full) --- 458 '''}) 459 header_output += MicroLeaDeclare.subst(iop) 460 decoder_output += MicroLdStOpConstructor.subst(iop) 461 exec_output += MicroLeaExecute.subst(iop) 462 463 class LeaOp(LdStOp): 464 def __init__(self, data, segment, addr, disp = 0, 465 dataSize="env.dataSize", addressSize="env.addressSize"): |
459 super(LeaOp, self).__init__(data, segment, 460 addr, disp, dataSize, addressSize, "0", False, False) | 466 super(LeaOp, self).__init__(data, segment, addr, disp, 467 dataSize, addressSize, "0", False, False, False) |
461 self.className = "Lea" 462 self.mnemonic = "lea" 463 464 microopClasses["lea"] = LeaOp 465 466 467 iop = InstObjParams("tia", "Tia", 'X86ISA::LdStOp', 468 {"code": "xc->demapPage(EA, 0);", 469 "ea_code": calculateEA}) 470 header_output += MicroLeaDeclare.subst(iop) 471 decoder_output += MicroLdStOpConstructor.subst(iop) 472 exec_output += MicroLeaExecute.subst(iop) 473 474 class TiaOp(LdStOp): 475 def __init__(self, segment, addr, disp = 0, 476 dataSize="env.dataSize", 477 addressSize="env.addressSize"): 478 super(TiaOp, self).__init__("InstRegIndex(NUM_INTREGS)", segment, | 468 self.className = "Lea" 469 self.mnemonic = "lea" 470 471 microopClasses["lea"] = LeaOp 472 473 474 iop = InstObjParams("tia", "Tia", 'X86ISA::LdStOp', 475 {"code": "xc->demapPage(EA, 0);", 476 "ea_code": calculateEA}) 477 header_output += MicroLeaDeclare.subst(iop) 478 decoder_output += MicroLdStOpConstructor.subst(iop) 479 exec_output += MicroLeaExecute.subst(iop) 480 481 class TiaOp(LdStOp): 482 def __init__(self, segment, addr, disp = 0, 483 dataSize="env.dataSize", 484 addressSize="env.addressSize"): 485 super(TiaOp, self).__init__("InstRegIndex(NUM_INTREGS)", segment, |
479 addr, disp, dataSize, addressSize, "0", False, False) | 486 addr, disp, dataSize, addressSize, "0", False, False, 487 False) |
480 self.className = "Tia" 481 self.mnemonic = "tia" 482 483 microopClasses["tia"] = TiaOp 484 485 class CdaOp(LdStOp): 486 def __init__(self, segment, addr, disp = 0, 487 dataSize="env.dataSize", 488 addressSize="env.addressSize", atCPL0=False): 489 super(CdaOp, self).__init__("InstRegIndex(NUM_INTREGS)", segment, 490 addr, disp, dataSize, addressSize, "Request::NO_ACCESS", | 488 self.className = "Tia" 489 self.mnemonic = "tia" 490 491 microopClasses["tia"] = TiaOp 492 493 class CdaOp(LdStOp): 494 def __init__(self, segment, addr, disp = 0, 495 dataSize="env.dataSize", 496 addressSize="env.addressSize", atCPL0=False): 497 super(CdaOp, self).__init__("InstRegIndex(NUM_INTREGS)", segment, 498 addr, disp, dataSize, addressSize, "Request::NO_ACCESS", |
491 atCPL0, False) | 499 atCPL0, False, False) |
492 self.className = "Cda" 493 self.mnemonic = "cda" 494 495 microopClasses["cda"] = CdaOp 496}}; 497 | 500 self.className = "Cda" 501 self.mnemonic = "cda" 502 503 microopClasses["cda"] = CdaOp 504}}; 505 |