| ldstop.isa (5920:5a9c976270d6) | ldstop.isa (5965:71f8d7c12619) |
|---|---|
| 1// Copyright (c) 2008 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright --- 361 unchanged lines hidden (view full) --- 370 self.segment = segment 371 self.dataSize = dataSize 372 self.addressSize = addressSize 373 self.memFlags = baseFlags 374 if atCPL0: 375 self.memFlags += " | (CPL0FlagBit << FlagShift)" 376 if prefetch: 377 self.memFlags += " | Request::PF_EXCLUSIVE" | 1// Copyright (c) 2008 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright --- 361 unchanged lines hidden (view full) --- 370 self.segment = segment 371 self.dataSize = dataSize 372 self.addressSize = addressSize 373 self.memFlags = baseFlags 374 if atCPL0: 375 self.memFlags += " | (CPL0FlagBit << FlagShift)" 376 if prefetch: 377 self.memFlags += " | Request::PF_EXCLUSIVE" |
| 378 self.memFlags += " | (machInst.legacy.addr ? " + \ 379 "(AddrSizeFlagBit << FlagShift) : 0)" |
|
| 378 379 def getAllocator(self, *microFlags): 380 allocator = '''new %(class_name)s(machInst, macrocodeBlock 381 %(flags)s, %(scale)s, %(index)s, %(base)s, 382 %(disp)s, %(segment)s, %(data)s, 383 %(dataSize)s, %(addressSize)s, %(memFlags)s)''' % { 384 "class_name" : self.className, 385 "flags" : self.microFlagsText(microFlags), --- 48 unchanged lines hidden (view full) --- 434 microopClasses[name] = LoadOp 435 436 defineMicroLoadOp('Ld', 'Data = merge(Data, Mem, dataSize);') 437 defineMicroLoadOp('Ldst', 'Data = merge(Data, Mem, dataSize);', 438 'X86ISA::StoreCheck') 439 defineMicroLoadOp('Ldfp', 'FpData.uqw = Mem;') 440 441 def defineMicroStoreOp(mnemonic, code, \ | 380 381 def getAllocator(self, *microFlags): 382 allocator = '''new %(class_name)s(machInst, macrocodeBlock 383 %(flags)s, %(scale)s, %(index)s, %(base)s, 384 %(disp)s, %(segment)s, %(data)s, 385 %(dataSize)s, %(addressSize)s, %(memFlags)s)''' % { 386 "class_name" : self.className, 387 "flags" : self.microFlagsText(microFlags), --- 48 unchanged lines hidden (view full) --- 436 microopClasses[name] = LoadOp 437 438 defineMicroLoadOp('Ld', 'Data = merge(Data, Mem, dataSize);') 439 defineMicroLoadOp('Ldst', 'Data = merge(Data, Mem, dataSize);', 440 'X86ISA::StoreCheck') 441 defineMicroLoadOp('Ldfp', 'FpData.uqw = Mem;') 442 443 def defineMicroStoreOp(mnemonic, code, \ |
| 442 postCode="", completeCode="", mem_flags=0): | 444 postCode="", completeCode="", mem_flags="0"): |
| 443 global header_output 444 global decoder_output 445 global exec_output 446 global microopClasses 447 Name = mnemonic 448 name = mnemonic.lower() 449 450 # Build up the all register version of this micro op --- 78 unchanged lines hidden --- | 445 global header_output 446 global decoder_output 447 global exec_output 448 global microopClasses 449 Name = mnemonic 450 name = mnemonic.lower() 451 452 # Build up the all register version of this micro op --- 78 unchanged lines hidden --- |