Cross Reference: /gem5/src/arch/x86/isa/microops/ldstop.isa

1// Copyright (c) 2008 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

--- 141 unchanged lines hidden (view full) ---

150
151 %(op_decl)s;
152 %(op_rd)s;
153 %(ea_code)s;
154 DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
155
156 fault = read(xc, EA, Mem, memFlags);
157

158 if(fault == NoFault)
159 {

158 if (fault == NoFault) {

160 %(code)s;

159 %(code)s;

160 } else if (memFlags & Request::PF_EXCLUSIVE) {
161 // For prefetches, ignore any faults/exceptions.
162 return NoFault;

161 }
162 if(fault == NoFault)
163 {
164 %(op_wb)s;
165 }
166
167 return fault;
168 }

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356 {
357 buildMe();
358 }
359}};
360
361let {{
362 class LdStOp(X86Microop):
363 def __init__(self, data, segment, addr, disp,

163 }
164 if(fault == NoFault)
165 {
166 %(op_wb)s;
167 }
168
169 return fault;
170 }

--- 187 unchanged lines hidden (view full) ---

358 {
359 buildMe();
360 }
361}};
362
363let {{
364 class LdStOp(X86Microop):
365 def __init__(self, data, segment, addr, disp,

364 dataSize, addressSize, baseFlags, atCPL0):

366 dataSize, addressSize, baseFlags, atCPL0, prefetch):

365 self.data = data
366 [self.scale, self.index, self.base] = addr
367 self.disp = disp
368 self.segment = segment
369 self.dataSize = dataSize
370 self.addressSize = addressSize
371 self.memFlags = baseFlags
372 if atCPL0:
373 self.memFlags += " | (CPL0FlagBit << FlagShift)"

367 self.data = data
368 [self.scale, self.index, self.base] = addr
369 self.disp = disp
370 self.segment = segment
371 self.dataSize = dataSize
372 self.addressSize = addressSize
373 self.memFlags = baseFlags
374 if atCPL0:
375 self.memFlags += " | (CPL0FlagBit << FlagShift)"

376 if prefetch:
377 self.memFlags += " | Request::PF_EXCLUSIVE"

374
375 def getAllocator(self, *microFlags):
376 allocator = '''new %(class_name)s(machInst, macrocodeBlock
377 %(flags)s, %(scale)s, %(index)s, %(base)s,
378 %(disp)s, %(segment)s, %(data)s,
379 %(dataSize)s, %(addressSize)s, %(memFlags)s)''' % {
380 "class_name" : self.className,
381 "flags" : self.microFlagsText(microFlags),

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415 exec_output += MicroLoadExecute.subst(iop)
416 exec_output += MicroLoadInitiateAcc.subst(iop)
417 exec_output += MicroLoadCompleteAcc.subst(iop)
418
419 class LoadOp(LdStOp):
420 def __init__(self, data, segment, addr, disp = 0,
421 dataSize="env.dataSize",
422 addressSize="env.addressSize",

378
379 def getAllocator(self, *microFlags):
380 allocator = '''new %(class_name)s(machInst, macrocodeBlock
381 %(flags)s, %(scale)s, %(index)s, %(base)s,
382 %(disp)s, %(segment)s, %(data)s,
383 %(dataSize)s, %(addressSize)s, %(memFlags)s)''' % {
384 "class_name" : self.className,
385 "flags" : self.microFlagsText(microFlags),

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419 exec_output += MicroLoadExecute.subst(iop)
420 exec_output += MicroLoadInitiateAcc.subst(iop)
421 exec_output += MicroLoadCompleteAcc.subst(iop)
422
423 class LoadOp(LdStOp):
424 def __init__(self, data, segment, addr, disp = 0,
425 dataSize="env.dataSize",
426 addressSize="env.addressSize",

423 atCPL0=False):

427 atCPL0=False, prefetch=False):

424 super(LoadOp, self).__init__(data, segment, addr,

428 super(LoadOp, self).__init__(data, segment, addr,

425 disp, dataSize, addressSize, mem_flags, atCPL0)

429 disp, dataSize, addressSize, mem_flags,
430 atCPL0, prefetch)

426 self.className = Name
427 self.mnemonic = name
428
429 microopClasses[name] = LoadOp
430
431 defineMicroLoadOp('Ld', 'Data = merge(Data, Mem, dataSize);')
432 defineMicroLoadOp('Ldst', 'Data = merge(Data, Mem, dataSize);',
433 'X86ISA::StoreCheck')

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455 exec_output += MicroStoreCompleteAcc.subst(iop)
456
457 class StoreOp(LdStOp):
458 def __init__(self, data, segment, addr, disp = 0,
459 dataSize="env.dataSize",
460 addressSize="env.addressSize",
461 atCPL0=False):
462 super(StoreOp, self).__init__(data, segment, addr,

431 self.className = Name
432 self.mnemonic = name
433
434 microopClasses[name] = LoadOp
435
436 defineMicroLoadOp('Ld', 'Data = merge(Data, Mem, dataSize);')
437 defineMicroLoadOp('Ldst', 'Data = merge(Data, Mem, dataSize);',
438 'X86ISA::StoreCheck')

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460 exec_output += MicroStoreCompleteAcc.subst(iop)
461
462 class StoreOp(LdStOp):
463 def __init__(self, data, segment, addr, disp = 0,
464 dataSize="env.dataSize",
465 addressSize="env.addressSize",
466 atCPL0=False):
467 super(StoreOp, self).__init__(data, segment, addr,

463 disp, dataSize, addressSize, mem_flags, atCPL0)

468 disp, dataSize, addressSize, mem_flags, atCPL0, False)

464 self.className = Name
465 self.mnemonic = name
466
467 microopClasses[name] = StoreOp
468
469 defineMicroStoreOp('St', 'Mem = pick(Data, 2, dataSize);')
470 defineMicroStoreOp('Stfp', 'Mem = FpData.uqw;')
471 defineMicroStoreOp('Stupd', 'Mem = pick(Data, 2, dataSize);',

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479 header_output += MicroLeaDeclare.subst(iop)
480 decoder_output += MicroLdStOpConstructor.subst(iop)
481 exec_output += MicroLeaExecute.subst(iop)
482
483 class LeaOp(LdStOp):
484 def __init__(self, data, segment, addr, disp = 0,
485 dataSize="env.dataSize", addressSize="env.addressSize"):
486 super(LeaOp, self).__init__(data, segment,

469 self.className = Name
470 self.mnemonic = name
471
472 microopClasses[name] = StoreOp
473
474 defineMicroStoreOp('St', 'Mem = pick(Data, 2, dataSize);')
475 defineMicroStoreOp('Stfp', 'Mem = FpData.uqw;')
476 defineMicroStoreOp('Stupd', 'Mem = pick(Data, 2, dataSize);',

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484 header_output += MicroLeaDeclare.subst(iop)
485 decoder_output += MicroLdStOpConstructor.subst(iop)
486 exec_output += MicroLeaExecute.subst(iop)
487
488 class LeaOp(LdStOp):
489 def __init__(self, data, segment, addr, disp = 0,
490 dataSize="env.dataSize", addressSize="env.addressSize"):
491 super(LeaOp, self).__init__(data, segment,

487 addr, disp, dataSize, addressSize, "0", False)

492 addr, disp, dataSize, addressSize, "0", False, False)

488 self.className = "Lea"
489 self.mnemonic = "lea"
490
491 microopClasses["lea"] = LeaOp
492
493
494 iop = InstObjParams("tia", "Tia", 'X86ISA::LdStOp',
495 {"code": "xc->demapPage(EA, 0);",
496 "ea_code": calculateEA})
497 header_output += MicroLeaDeclare.subst(iop)
498 decoder_output += MicroLdStOpConstructor.subst(iop)
499 exec_output += MicroLeaExecute.subst(iop)
500
501 class TiaOp(LdStOp):
502 def __init__(self, segment, addr, disp = 0,
503 dataSize="env.dataSize",
504 addressSize="env.addressSize"):
505 super(TiaOp, self).__init__("NUM_INTREGS", segment,

493 self.className = "Lea"
494 self.mnemonic = "lea"
495
496 microopClasses["lea"] = LeaOp
497
498
499 iop = InstObjParams("tia", "Tia", 'X86ISA::LdStOp',
500 {"code": "xc->demapPage(EA, 0);",
501 "ea_code": calculateEA})
502 header_output += MicroLeaDeclare.subst(iop)
503 decoder_output += MicroLdStOpConstructor.subst(iop)
504 exec_output += MicroLeaExecute.subst(iop)
505
506 class TiaOp(LdStOp):
507 def __init__(self, segment, addr, disp = 0,
508 dataSize="env.dataSize",
509 addressSize="env.addressSize"):
510 super(TiaOp, self).__init__("NUM_INTREGS", segment,

506 addr, disp, dataSize, addressSize, "0", False)

511 addr, disp, dataSize, addressSize, "0", False, False)

507 self.className = "Tia"
508 self.mnemonic = "tia"
509
510 microopClasses["tia"] = TiaOp
511
512 class CdaOp(LdStOp):
513 def __init__(self, segment, addr, disp = 0,
514 dataSize="env.dataSize",
515 addressSize="env.addressSize", atCPL0=False):
516 super(CdaOp, self).__init__("NUM_INTREGS", segment,

512 self.className = "Tia"
513 self.mnemonic = "tia"
514
515 microopClasses["tia"] = TiaOp
516
517 class CdaOp(LdStOp):
518 def __init__(self, segment, addr, disp = 0,
519 dataSize="env.dataSize",
520 addressSize="env.addressSize", atCPL0=False):
521 super(CdaOp, self).__init__("NUM_INTREGS", segment,

517 addr, disp, dataSize, addressSize, "0", atCPL0)

522 addr, disp, dataSize, addressSize, "0", atCPL0, False)