ldstop.isa (4720:15cb65a86e5a) ldstop.isa (4767:5e55d650692e)
1// Copyright (c) 2007 The Hewlett-Packard Development Company
2// All rights reserved.
3//
4// Redistribution and use of this software in source and binary forms,
5// with or without modification, are permitted provided that the
6// following conditions are met:
7//
8// The software must be used only for Non-Commercial Use which means any

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118 Fault fault = NoFault;
119 Addr EA;
120
121 %(op_decl)s;
122 %(op_rd)s;
123 %(ea_code)s;
124 DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
125
1// Copyright (c) 2007 The Hewlett-Packard Development Company
2// All rights reserved.
3//
4// Redistribution and use of this software in source and binary forms,
5// with or without modification, are permitted provided that the
6// following conditions are met:
7//
8// The software must be used only for Non-Commercial Use which means any

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118 Fault fault = NoFault;
119 Addr EA;
120
121 %(op_decl)s;
122 %(op_rd)s;
123 %(ea_code)s;
124 DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
125
126 unsigned flags = 0;
127 switch(dataSize)
128 {
129 case 1:
130 fault = xc->read(EA, (uint8_t&)Mem, flags);
131 break;
132 case 2:
133 fault = xc->read(EA, (uint16_t&)Mem, flags);
134 break;
135 case 4:
136 fault = xc->read(EA, (uint32_t&)Mem, flags);
137 break;
138 case 8:
139 fault = xc->read(EA, (uint64_t&)Mem, flags);
140 break;
141 default:
142 panic("Bad operand size!\n");
143 }
126 fault = read(xc, EA, Mem, 0);
127 int offset = EA & (dataSize - 1);
128 Mem = bits(Mem, (offset + dataSize) * 8 - 1, offset * 8);
144
145 if(fault == NoFault)
146 {
147 %(code)s;
148 }
149 if(fault == NoFault)
150 {
151 %(op_wb)s;

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162 Fault fault = NoFault;
163 Addr EA;
164
165 %(op_decl)s;
166 %(op_rd)s;
167 %(ea_code)s;
168 DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
169
129
130 if(fault == NoFault)
131 {
132 %(code)s;
133 }
134 if(fault == NoFault)
135 {
136 %(op_wb)s;

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147 Fault fault = NoFault;
148 Addr EA;
149
150 %(op_decl)s;
151 %(op_rd)s;
152 %(ea_code)s;
153 DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
154
170 unsigned flags = 0;
171 switch(dataSize)
172 {
173 case 1:
174 fault = xc->read(EA, (uint8_t&)Mem, flags);
175 break;
176 case 2:
177 fault = xc->read(EA, (uint16_t&)Mem, flags);
178 break;
179 case 4:
180 fault = xc->read(EA, (uint32_t&)Mem, flags);
181 break;
182 case 8:
183 fault = xc->read(EA, (uint64_t&)Mem, flags);
184 break;
185 default:
186 panic("Bad operand size!\n");
187 }
155 int offset = EA & (dataSize - 1);
156 fault = read(xc, EA, Mem, offset);
188
189 return fault;
190 }
191}};
192
193def template MicroLoadCompleteAcc {{
194 Fault %(class_name)s::completeAcc(PacketPtr pkt,
195 %(CPU_exec_context)s * xc,
196 Trace::InstRecord * traceData) const
197 {
198 Fault fault = NoFault;
199
200 %(op_decl)s;
201 %(op_rd)s;
202
203 Mem = pkt->get<typeof(Mem)>();
157
158 return fault;
159 }
160}};
161
162def template MicroLoadCompleteAcc {{
163 Fault %(class_name)s::completeAcc(PacketPtr pkt,
164 %(CPU_exec_context)s * xc,
165 Trace::InstRecord * traceData) const
166 {
167 Fault fault = NoFault;
168
169 %(op_decl)s;
170 %(op_rd)s;
171
172 Mem = pkt->get<typeof(Mem)>();
173 int offset = pkt->flags;
174 Mem = bits(Mem, (offset + dataSize) * 8 - 1, offset * 8);
204 %(code)s;
205
206 if(fault == NoFault)
207 {
208 %(op_wb)s;
209 }
210
211 return fault;

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225 %(op_rd)s;
226 %(ea_code)s;
227 DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
228
229 %(code)s;
230
231 if(fault == NoFault)
232 {
175 %(code)s;
176
177 if(fault == NoFault)
178 {
179 %(op_wb)s;
180 }
181
182 return fault;

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196 %(op_rd)s;
197 %(ea_code)s;
198 DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
199
200 %(code)s;
201
202 if(fault == NoFault)
203 {
233 unsigned flags = 0;
234 uint64_t *res = 0;
235 switch(dataSize)
204 Mem = Mem << ((EA & (dataSize - 1)) * 8);
205 fault = write(xc, Mem, EA, 0);
206 if(fault == NoFault)
236 {
207 {
237 case 1:
238 fault = xc->write((uint8_t&)Mem, EA, flags, res);
239 break;
240 case 2:
241 fault = xc->write((uint16_t&)Mem, EA, flags, res);
242 break;
243 case 4:
244 fault = xc->write((uint32_t&)Mem, EA, flags, res);
245 break;
246 case 8:
247 fault = xc->write((uint64_t&)Mem, EA, flags, res);
248 break;
249 default:
250 panic("Bad operand size!\n");
208 %(op_wb)s;
251 }
252 }
209 }
210 }
253 if(fault == NoFault)
254 {
255 %(op_wb)s;
256 }
257
258 return fault;
259 }
260}};
261
262def template MicroStoreInitiateAcc {{
263 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s * xc,
264 Trace::InstRecord * traceData) const

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270 %(op_rd)s;
271 %(ea_code)s;
272 DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
273
274 %(code)s;
275
276 if(fault == NoFault)
277 {
211
212 return fault;
213 }
214}};
215
216def template MicroStoreInitiateAcc {{
217 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s * xc,
218 Trace::InstRecord * traceData) const

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224 %(op_rd)s;
225 %(ea_code)s;
226 DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
227
228 %(code)s;
229
230 if(fault == NoFault)
231 {
278 unsigned flags = 0;
279 uint64_t *res = 0;
280 switch(dataSize)
232 Mem = Mem << ((EA & (dataSize - 1)) * 8);
233 fault = write(xc, Mem, EA, 0);
234 if(fault == NoFault)
281 {
235 {
282 case 1:
283 fault = xc->write((uint8_t&)Mem, EA, flags, res);
284 break;
285 case 2:
286 fault = xc->write((uint16_t&)Mem, EA, flags, res);
287 break;
288 case 4:
289 fault = xc->write((uint32_t&)Mem, EA, flags, res);
290 break;
291 case 8:
292 fault = xc->write((uint64_t&)Mem, EA, flags, res);
293 break;
294 default:
295 panic("Bad operand size!\n");
236 %(op_wb)s;
296 }
297 }
237 }
238 }
298 if(fault == NoFault)
299 {
300 %(op_wb)s;
301 }
302 return fault;
303 }
304}};
305
306def template MicroStoreCompleteAcc {{
307 Fault %(class_name)s::completeAcc(PacketPtr, %(CPU_exec_context)s * xc,
308 Trace::InstRecord * traceData) const
309 {

--- 195 unchanged lines hidden --- 		239 return fault;
240 }
241}};
242
243def template MicroStoreCompleteAcc {{
244 Fault %(class_name)s::completeAcc(PacketPtr, %(CPU_exec_context)s * xc,
245 Trace::InstRecord * traceData) const
246 {

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