ldstop.isa (12463:84f365522633) ldstop.isa (12682:dfc3bb0db088)
1// Copyright (c) 2007-2008 The Hewlett-Packard Development Company
2// Copyright (c) 2015 Advanced Micro Devices, Inc.
3// All rights reserved.
4//
5// The license below extends only to copyright in the software and shall
6// not be construed as granting a license to any other intellectual
7// property including but not limited to intellectual property relating
8// to a hardware implementation of the functionality of the software

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290 %(constructor)s;
291 }
292}};
293
294let {{
295 class LdStOp(X86Microop):
296 def __init__(self, data, segment, addr, disp,
297 dataSize, addressSize, baseFlags, atCPL0, prefetch, nonSpec,
1// Copyright (c) 2007-2008 The Hewlett-Packard Development Company
2// Copyright (c) 2015 Advanced Micro Devices, Inc.
3// All rights reserved.
4//
5// The license below extends only to copyright in the software and shall
6// not be construed as granting a license to any other intellectual
7// property including but not limited to intellectual property relating
8// to a hardware implementation of the functionality of the software

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290 %(constructor)s;
291 }
292}};
293
294let {{
295 class LdStOp(X86Microop):
296 def __init__(self, data, segment, addr, disp,
297 dataSize, addressSize, baseFlags, atCPL0, prefetch, nonSpec,
298 implicitStack):
298 implicitStack, uncacheable):
299 self.data = data
300 [self.scale, self.index, self.base] = addr
301 self.disp = disp
302 self.segment = segment
303 self.dataSize = dataSize
304 self.addressSize = addressSize
305 self.memFlags = baseFlags
306 if atCPL0:
307 self.memFlags += " | (CPL0FlagBit << FlagShift)"
308 self.instFlags = ""
309 if prefetch:
310 self.memFlags += " | Request::PREFETCH"
311 self.instFlags += " | (1ULL << StaticInst::IsDataPrefetch)"
312 if nonSpec:
313 self.instFlags += " | (1ULL << StaticInst::IsNonSpeculative)"
299 self.data = data
300 [self.scale, self.index, self.base] = addr
301 self.disp = disp
302 self.segment = segment
303 self.dataSize = dataSize
304 self.addressSize = addressSize
305 self.memFlags = baseFlags
306 if atCPL0:
307 self.memFlags += " | (CPL0FlagBit << FlagShift)"
308 self.instFlags = ""
309 if prefetch:
310 self.memFlags += " | Request::PREFETCH"
311 self.instFlags += " | (1ULL << StaticInst::IsDataPrefetch)"
312 if nonSpec:
313 self.instFlags += " | (1ULL << StaticInst::IsNonSpeculative)"
314 if uncacheable:
315 self.instFlags += " | (Request::UNCACHEABLE)"
314 # For implicit stack operations, we should use *not* use the
315 # alternative addressing mode for loads/stores if the prefix is set
316 if not implicitStack:
317 self.memFlags += " | (machInst.legacy.addr ? " + \
318 "(AddrSizeFlagBit << FlagShift) : 0)"
319
320 def getAllocator(self, microFlags):
321 allocator = '''new %(class_name)s(machInst, macrocodeBlock,

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330 "segment" : self.segment, "data" : self.data,
331 "dataSize" : self.dataSize, "addressSize" : self.addressSize,
332 "memFlags" : self.memFlags}
333 return allocator
334
335 class BigLdStOp(X86Microop):
336 def __init__(self, data, segment, addr, disp,
337 dataSize, addressSize, baseFlags, atCPL0, prefetch, nonSpec,
316 # For implicit stack operations, we should use *not* use the
317 # alternative addressing mode for loads/stores if the prefix is set
318 if not implicitStack:
319 self.memFlags += " | (machInst.legacy.addr ? " + \
320 "(AddrSizeFlagBit << FlagShift) : 0)"
321
322 def getAllocator(self, microFlags):
323 allocator = '''new %(class_name)s(machInst, macrocodeBlock,

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332 "segment" : self.segment, "data" : self.data,
333 "dataSize" : self.dataSize, "addressSize" : self.addressSize,
334 "memFlags" : self.memFlags}
335 return allocator
336
337 class BigLdStOp(X86Microop):
338 def __init__(self, data, segment, addr, disp,
339 dataSize, addressSize, baseFlags, atCPL0, prefetch, nonSpec,
338 implicitStack):
340 implicitStack, uncacheable):
339 self.data = data
340 [self.scale, self.index, self.base] = addr
341 self.disp = disp
342 self.segment = segment
343 self.dataSize = dataSize
344 self.addressSize = addressSize
345 self.memFlags = baseFlags
346 if atCPL0:
347 self.memFlags += " | (CPL0FlagBit << FlagShift)"
348 self.instFlags = ""
349 if prefetch:
350 self.memFlags += " | Request::PREFETCH"
351 self.instFlags += " | (1ULL << StaticInst::IsDataPrefetch)"
352 if nonSpec:
353 self.instFlags += " | (1ULL << StaticInst::IsNonSpeculative)"
341 self.data = data
342 [self.scale, self.index, self.base] = addr
343 self.disp = disp
344 self.segment = segment
345 self.dataSize = dataSize
346 self.addressSize = addressSize
347 self.memFlags = baseFlags
348 if atCPL0:
349 self.memFlags += " | (CPL0FlagBit << FlagShift)"
350 self.instFlags = ""
351 if prefetch:
352 self.memFlags += " | Request::PREFETCH"
353 self.instFlags += " | (1ULL << StaticInst::IsDataPrefetch)"
354 if nonSpec:
355 self.instFlags += " | (1ULL << StaticInst::IsNonSpeculative)"
356 if uncacheable:
357 self.instFlags += " | (Request::UNCACHEABLE)"
354 # For implicit stack operations, we should use *not* use the
355 # alternative addressing mode for loads/stores if the prefix is set
356 if not implicitStack:
357 self.memFlags += " | (machInst.legacy.addr ? " + \
358 "(AddrSizeFlagBit << FlagShift) : 0)"
359
360 def getAllocator(self, microFlags):
361 allocString = '''

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378 "segment" : self.segment, "data" : self.data,
379 "dataSize" : self.dataSize, "addressSize" : self.addressSize,
380 "memFlags" : self.memFlags}
381 return allocator
382
383 class LdStSplitOp(LdStOp):
384 def __init__(self, data, segment, addr, disp,
385 dataSize, addressSize, baseFlags, atCPL0, prefetch, nonSpec,
358 # For implicit stack operations, we should use *not* use the
359 # alternative addressing mode for loads/stores if the prefix is set
360 if not implicitStack:
361 self.memFlags += " | (machInst.legacy.addr ? " + \
362 "(AddrSizeFlagBit << FlagShift) : 0)"
363
364 def getAllocator(self, microFlags):
365 allocString = '''

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382 "segment" : self.segment, "data" : self.data,
383 "dataSize" : self.dataSize, "addressSize" : self.addressSize,
384 "memFlags" : self.memFlags}
385 return allocator
386
387 class LdStSplitOp(LdStOp):
388 def __init__(self, data, segment, addr, disp,
389 dataSize, addressSize, baseFlags, atCPL0, prefetch, nonSpec,
386 implicitStack):
390 implicitStack, uncacheable):
387 super(LdStSplitOp, self).__init__(0, segment, addr, disp,
388 dataSize, addressSize, baseFlags, atCPL0, prefetch, nonSpec,
391 super(LdStSplitOp, self).__init__(0, segment, addr, disp,
392 dataSize, addressSize, baseFlags, atCPL0, prefetch, nonSpec,
389 implicitStack)
393 implicitStack, uncacheable)
390 (self.dataLow, self.dataHi) = data
391
392 def getAllocator(self, microFlags):
393 allocString = '''(StaticInstPtr)(new %(class_name)s(machInst,
394 macrocodeBlock, %(flags)s, %(scale)s, %(index)s,
395 %(base)s, %(disp)s, %(segment)s,
396 %(dataLow)s, %(dataHi)s,
397 %(dataSize)s, %(addressSize)s, %(memFlags)s))

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461 base = LdStOp
462 if big:
463 base = BigLdStOp
464 class LoadOp(base):
465 def __init__(self, data, segment, addr, disp = 0,
466 dataSize="env.dataSize",
467 addressSize=addressSize,
468 atCPL0=False, prefetch=False, nonSpec=nonSpec,
394 (self.dataLow, self.dataHi) = data
395
396 def getAllocator(self, microFlags):
397 allocString = '''(StaticInstPtr)(new %(class_name)s(machInst,
398 macrocodeBlock, %(flags)s, %(scale)s, %(index)s,
399 %(base)s, %(disp)s, %(segment)s,
400 %(dataLow)s, %(dataHi)s,
401 %(dataSize)s, %(addressSize)s, %(memFlags)s))

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465 base = LdStOp
466 if big:
467 base = BigLdStOp
468 class LoadOp(base):
469 def __init__(self, data, segment, addr, disp = 0,
470 dataSize="env.dataSize",
471 addressSize=addressSize,
472 atCPL0=False, prefetch=False, nonSpec=nonSpec,
469 implicitStack=implicitStack):
473 implicitStack=implicitStack, uncacheable=False):
470 super(LoadOp, self).__init__(data, segment, addr,
471 disp, dataSize, addressSize, mem_flags,
474 super(LoadOp, self).__init__(data, segment, addr,
475 disp, dataSize, addressSize, mem_flags,
472 atCPL0, prefetch, nonSpec, implicitStack)
476 atCPL0, prefetch, nonSpec, implicitStack, uncacheable)
473 self.className = Name
474 self.mnemonic = name
475
476 microopClasses[name] = LoadOp
477
478 defineMicroLoadOp('Ld', 'Data = merge(Data, Mem, dataSize);',
479 'Data = Mem & mask(dataSize * 8);')
480 defineMicroLoadOp('Ldis', 'Data = merge(Data, Mem, dataSize);',

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542 exec_output += MicroLoadInitiateAcc.subst(iop)
543 exec_output += MicroLoadCompleteAcc.subst(iop)
544
545 class LoadOp(LdStSplitOp):
546 def __init__(self, data, segment, addr, disp = 0,
547 dataSize="env.dataSize",
548 addressSize="env.addressSize",
549 atCPL0=False, prefetch=False, nonSpec=nonSpec,
477 self.className = Name
478 self.mnemonic = name
479
480 microopClasses[name] = LoadOp
481
482 defineMicroLoadOp('Ld', 'Data = merge(Data, Mem, dataSize);',
483 'Data = Mem & mask(dataSize * 8);')
484 defineMicroLoadOp('Ldis', 'Data = merge(Data, Mem, dataSize);',

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546 exec_output += MicroLoadInitiateAcc.subst(iop)
547 exec_output += MicroLoadCompleteAcc.subst(iop)
548
549 class LoadOp(LdStSplitOp):
550 def __init__(self, data, segment, addr, disp = 0,
551 dataSize="env.dataSize",
552 addressSize="env.addressSize",
553 atCPL0=False, prefetch=False, nonSpec=nonSpec,
550 implicitStack=False):
554 implicitStack=False, uncacheable=False):
551 super(LoadOp, self).__init__(data, segment, addr,
552 disp, dataSize, addressSize, mem_flags,
555 super(LoadOp, self).__init__(data, segment, addr,
556 disp, dataSize, addressSize, mem_flags,
553 atCPL0, prefetch, nonSpec, implicitStack)
557 atCPL0, prefetch, nonSpec, implicitStack, uncacheable)
554 self.className = Name
555 self.mnemonic = name
556
557 microopClasses[name] = LoadOp
558
559 code = '''
560 DataLow = Mem_u2qw[0];
561 DataHi = Mem_u2qw[1];

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596 addressSize = "env.stackSize"
597 else:
598 addressSize = "env.addressSize"
599
600 class StoreOp(LdStOp):
601 def __init__(self, data, segment, addr, disp = 0,
602 dataSize="env.dataSize",
603 addressSize=addressSize,
558 self.className = Name
559 self.mnemonic = name
560
561 microopClasses[name] = LoadOp
562
563 code = '''
564 DataLow = Mem_u2qw[0];
565 DataHi = Mem_u2qw[1];

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600 addressSize = "env.stackSize"
601 else:
602 addressSize = "env.addressSize"
603
604 class StoreOp(LdStOp):
605 def __init__(self, data, segment, addr, disp = 0,
606 dataSize="env.dataSize",
607 addressSize=addressSize,
604 atCPL0=False, nonSpec=False, implicitStack=implicitStack):
608 atCPL0=False, nonSpec=False, implicitStack=implicitStack,
609 uncacheable=False):
605 super(StoreOp, self).__init__(data, segment, addr, disp,
606 dataSize, addressSize, mem_flags, atCPL0, False,
610 super(StoreOp, self).__init__(data, segment, addr, disp,
611 dataSize, addressSize, mem_flags, atCPL0, False,
607 nonSpec, implicitStack)
612 nonSpec, implicitStack, uncacheable)
608 self.className = Name
609 self.mnemonic = name
610
611 microopClasses[name] = StoreOp
612
613 defineMicroStoreOp('St', 'Mem = pick(Data, 2, dataSize);')
614 defineMicroStoreOp('Stis', 'Mem = pick(Data, 2, dataSize);',
615 implicitStack=True)

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660 exec_output += MicroStoreExecute.subst(iop)
661 exec_output += MicroStoreInitiateAcc.subst(iop)
662 exec_output += MicroStoreCompleteAcc.subst(iop)
663
664 class StoreOp(LdStSplitOp):
665 def __init__(self, data, segment, addr, disp = 0,
666 dataSize="env.dataSize",
667 addressSize="env.addressSize",
613 self.className = Name
614 self.mnemonic = name
615
616 microopClasses[name] = StoreOp
617
618 defineMicroStoreOp('St', 'Mem = pick(Data, 2, dataSize);')
619 defineMicroStoreOp('Stis', 'Mem = pick(Data, 2, dataSize);',
620 implicitStack=True)

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665 exec_output += MicroStoreExecute.subst(iop)
666 exec_output += MicroStoreInitiateAcc.subst(iop)
667 exec_output += MicroStoreCompleteAcc.subst(iop)
668
669 class StoreOp(LdStSplitOp):
670 def __init__(self, data, segment, addr, disp = 0,
671 dataSize="env.dataSize",
672 addressSize="env.addressSize",
668 atCPL0=False, nonSpec=False, implicitStack=False):
673 atCPL0=False, nonSpec=False, implicitStack=False,
674 uncacheable=False):
669 super(StoreOp, self).__init__(data, segment, addr, disp,
670 dataSize, addressSize, mem_flags, atCPL0, False,
675 super(StoreOp, self).__init__(data, segment, addr, disp,
676 dataSize, addressSize, mem_flags, atCPL0, False,
671 nonSpec, implicitStack)
677 nonSpec, implicitStack, uncacheable)
672 self.className = Name
673 self.mnemonic = name
674
675 microopClasses[name] = StoreOp
676
677 code = '''
678 Mem_u2qw[0] = DataLow;
679 Mem_u2qw[1] = DataHi;

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691 header_output += MicroLeaDeclare.subst(iop)
692 decoder_output += MicroLdStOpConstructor.subst(iop)
693 exec_output += MicroLeaExecute.subst(iop)
694
695 class LeaOp(LdStOp):
696 def __init__(self, data, segment, addr, disp = 0,
697 dataSize="env.dataSize", addressSize="env.addressSize"):
698 super(LeaOp, self).__init__(data, segment, addr, disp,
678 self.className = Name
679 self.mnemonic = name
680
681 microopClasses[name] = StoreOp
682
683 code = '''
684 Mem_u2qw[0] = DataLow;
685 Mem_u2qw[1] = DataHi;

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697 header_output += MicroLeaDeclare.subst(iop)
698 decoder_output += MicroLdStOpConstructor.subst(iop)
699 exec_output += MicroLeaExecute.subst(iop)
700
701 class LeaOp(LdStOp):
702 def __init__(self, data, segment, addr, disp = 0,
703 dataSize="env.dataSize", addressSize="env.addressSize"):
704 super(LeaOp, self).__init__(data, segment, addr, disp,
699 dataSize, addressSize, "0", False, False, False, False)
705 dataSize, addressSize, "0",
706 False, False, False, False, False)
700 self.className = "Lea"
701 self.mnemonic = "lea"
702
703 microopClasses["lea"] = LeaOp
704
705
706 iop = InstObjParams("tia", "Tia", 'X86ISA::LdStOp',
707 { "code": "xc->demapPage(EA, 0);",

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712 exec_output += MicroLeaExecute.subst(iop)
713
714 class TiaOp(LdStOp):
715 def __init__(self, segment, addr, disp = 0,
716 dataSize="env.dataSize",
717 addressSize="env.addressSize"):
718 super(TiaOp, self).__init__("InstRegIndex(NUM_INTREGS)", segment,
719 addr, disp, dataSize, addressSize, "0", False, False,
707 self.className = "Lea"
708 self.mnemonic = "lea"
709
710 microopClasses["lea"] = LeaOp
711
712
713 iop = InstObjParams("tia", "Tia", 'X86ISA::LdStOp',
714 { "code": "xc->demapPage(EA, 0);",

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719 exec_output += MicroLeaExecute.subst(iop)
720
721 class TiaOp(LdStOp):
722 def __init__(self, segment, addr, disp = 0,
723 dataSize="env.dataSize",
724 addressSize="env.addressSize"):
725 super(TiaOp, self).__init__("InstRegIndex(NUM_INTREGS)", segment,
726 addr, disp, dataSize, addressSize, "0", False, False,
720 False, False)
727 False, False, False)
721 self.className = "Tia"
722 self.mnemonic = "tia"
723
724 microopClasses["tia"] = TiaOp
725
726 class CdaOp(LdStOp):
727 def __init__(self, segment, addr, disp = 0,
728 dataSize="env.dataSize",
729 addressSize="env.addressSize", atCPL0=False):
730 super(CdaOp, self).__init__("InstRegIndex(NUM_INTREGS)", segment,
731 addr, disp, dataSize, addressSize, "Request::NO_ACCESS",
728 self.className = "Tia"
729 self.mnemonic = "tia"
730
731 microopClasses["tia"] = TiaOp
732
733 class CdaOp(LdStOp):
734 def __init__(self, segment, addr, disp = 0,
735 dataSize="env.dataSize",
736 addressSize="env.addressSize", atCPL0=False):
737 super(CdaOp, self).__init__("InstRegIndex(NUM_INTREGS)", segment,
738 addr, disp, dataSize, addressSize, "Request::NO_ACCESS",
732 atCPL0, False, False, False)
739 atCPL0, False, False, False, False)
733 self.className = "Cda"
734 self.mnemonic = "cda"
735
736 microopClasses["cda"] = CdaOp
737}};
740 self.className = "Cda"
741 self.mnemonic = "cda"
742
743 microopClasses["cda"] = CdaOp
744}};