ldstop.isa (12236:126ac9da6050) ldstop.isa (12384:481add71d2e4)
1// Copyright (c) 2007-2008 The Hewlett-Packard Development Company
2// Copyright (c) 2015 Advanced Micro Devices, Inc.
3// All rights reserved.
4//
5// The license below extends only to copyright in the software and shall
6// not be construed as granting a license to any other intellectual
7// property including but not limited to intellectual property relating
8// to a hardware implementation of the functionality of the software

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94 Fault fault = NoFault;
95 Addr EA;
96
97 %(op_decl)s;
98 %(op_rd)s;
99 %(ea_code)s;
100 DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
101
1// Copyright (c) 2007-2008 The Hewlett-Packard Development Company
2// Copyright (c) 2015 Advanced Micro Devices, Inc.
3// All rights reserved.
4//
5// The license below extends only to copyright in the software and shall
6// not be construed as granting a license to any other intellectual
7// property including but not limited to intellectual property relating
8// to a hardware implementation of the functionality of the software

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94 Fault fault = NoFault;
95 Addr EA;
96
97 %(op_decl)s;
98 %(op_rd)s;
99 %(ea_code)s;
100 DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
101
102 fault = readMemAtomic(xc, traceData, EA, Mem,
103 %(memDataSize)s, memFlags);
102 fault = readMemAtomic(xc, traceData, EA, Mem, dataSize, memFlags);
104
105 if (fault == NoFault) {
106 %(code)s;
107 } else if (memFlags & Request::PREFETCH) {
108 // For prefetches, ignore any faults/exceptions.
109 return NoFault;
110 }
111 if(fault == NoFault)

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140 Fault %(class_name)s::completeAcc(PacketPtr pkt, ExecContext * xc,
141 Trace::InstRecord * traceData) const
142 {
143 Fault fault = NoFault;
144
145 %(op_decl)s;
146 %(op_rd)s;
147
103
104 if (fault == NoFault) {
105 %(code)s;
106 } else if (memFlags & Request::PREFETCH) {
107 // For prefetches, ignore any faults/exceptions.
108 return NoFault;
109 }
110 if(fault == NoFault)

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139 Fault %(class_name)s::completeAcc(PacketPtr pkt, ExecContext * xc,
140 Trace::InstRecord * traceData) const
141 {
142 Fault fault = NoFault;
143
144 %(op_decl)s;
145 %(op_rd)s;
146
148 getMem(pkt, Mem, %(memDataSize)s, traceData);
147 getMem(pkt, Mem, dataSize, traceData);
149
150 %(code)s;
151
152 if(fault == NoFault)
153 {
154 %(op_wb)s;
155 }
156

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169 Addr EA;
170 %(op_decl)s;
171 %(op_rd)s;
172 %(ea_code)s;
173 DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
174
175 %(code)s;
176
148
149 %(code)s;
150
151 if(fault == NoFault)
152 {
153 %(op_wb)s;
154 }
155

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168 Addr EA;
169 %(op_decl)s;
170 %(op_rd)s;
171 %(ea_code)s;
172 DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
173
174 %(code)s;
175
177 if(fault == NoFault)
178 {
179 fault = writeMemAtomic(xc, traceData, Mem, %(memDataSize)s, EA,
180 memFlags, NULL);
181 if(fault == NoFault)
182 {
176 if (fault == NoFault) {
177 fault = writeMemAtomic(xc, traceData, Mem, dataSize, EA,
178 memFlags, NULL);
179 if (fault == NoFault) {
183 %(op_wb)s;
184 }
185 }
186
187 return fault;
188 }
189}};
190

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197 Addr EA;
198 %(op_decl)s;
199 %(op_rd)s;
200 %(ea_code)s;
201 DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
202
203 %(code)s;
204
180 %(op_wb)s;
181 }
182 }
183
184 return fault;
185 }
186}};
187

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194 Addr EA;
195 %(op_decl)s;
196 %(op_rd)s;
197 %(ea_code)s;
198 DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
199
200 %(code)s;
201
205 if(fault == NoFault)
206 {
207 fault = writeMemTiming(xc, traceData, Mem, %(memDataSize)s, EA,
208 memFlags, NULL);
202 if (fault == NoFault) {
203 fault = writeMemTiming(xc, traceData, Mem, dataSize, EA,
204 memFlags, NULL);
209 }
210 return fault;
211 }
212}};
213
214def template MicroStoreCompleteAcc {{
215 Fault %(class_name)s::completeAcc(PacketPtr pkt,
216 ExecContext * xc, Trace::InstRecord * traceData) const

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556 disp, dataSize, addressSize, mem_flags,
557 atCPL0, prefetch, nonSpec, implicitStack)
558 self.className = Name
559 self.mnemonic = name
560
561 microopClasses[name] = LoadOp
562
563 code = '''
205 }
206 return fault;
207 }
208}};
209
210def template MicroStoreCompleteAcc {{
211 Fault %(class_name)s::completeAcc(PacketPtr pkt,
212 ExecContext * xc, Trace::InstRecord * traceData) const

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552 disp, dataSize, addressSize, mem_flags,
553 atCPL0, prefetch, nonSpec, implicitStack)
554 self.className = Name
555 self.mnemonic = name
556
557 microopClasses[name] = LoadOp
558
559 code = '''
564 switch (dataSize) {
565 case 4:
566 DataLow = bits(Mem_u2qw[0], 31, 0);
567 DataHi = bits(Mem_u2qw[0], 63, 32);
568 break;
569 case 8:
570 DataLow = Mem_u2qw[0];
571 DataHi = Mem_u2qw[1];
572 break;
573 default:
574 panic("Unhandled data size %d in LdSplit.\\n", dataSize);
575 }'''
560 DataLow = Mem_u2qw[0];
561 DataHi = Mem_u2qw[1];
562 '''
576
577 defineMicroLoadSplitOp('LdSplit', code,
578 '(StoreCheck << FlagShift)')
579
580 defineMicroLoadSplitOp('LdSplitl', code,
581 '(StoreCheck << FlagShift) | Request::LOCKED_RMW',
582 nonSpec=True)
583

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678 dataSize, addressSize, mem_flags, atCPL0, False,
679 nonSpec, implicitStack)
680 self.className = Name
681 self.mnemonic = name
682
683 microopClasses[name] = StoreOp
684
685 code = '''
563
564 defineMicroLoadSplitOp('LdSplit', code,
565 '(StoreCheck << FlagShift)')
566
567 defineMicroLoadSplitOp('LdSplitl', code,
568 '(StoreCheck << FlagShift) | Request::LOCKED_RMW',
569 nonSpec=True)
570

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665 dataSize, addressSize, mem_flags, atCPL0, False,
666 nonSpec, implicitStack)
667 self.className = Name
668 self.mnemonic = name
669
670 microopClasses[name] = StoreOp
671
672 code = '''
686 switch (dataSize) {
687 case 4:
688 Mem_u2qw[0] = (DataHi << 32) | DataLow;
689 break;
690 case 8:
691 Mem_u2qw[0] = DataLow;
692 Mem_u2qw[1] = DataHi;
693 break;
694 default:
695 panic("Unhandled data size %d in StSplit.\\n", dataSize);
696 }'''
673 Mem_u2qw[0] = DataLow;
674 Mem_u2qw[1] = DataHi;
675 '''
697
698 defineMicroStoreSplitOp('StSplit', code);
699
700 defineMicroStoreSplitOp('StSplitul', code,
701 mem_flags='Request::LOCKED_RMW')
702
703 iop = InstObjParams("lea", "Lea", 'X86ISA::LdStOp',
704 { "code": "Data = merge(Data, EA, dataSize);",

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677 defineMicroStoreSplitOp('StSplit', code);
678
679 defineMicroStoreSplitOp('StSplitul', code,
680 mem_flags='Request::LOCKED_RMW')
681
682 iop = InstObjParams("lea", "Lea", 'X86ISA::LdStOp',
683 { "code": "Data = merge(Data, EA, dataSize);",

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