ldstop.isa (11329:82bb3ee706b3) ldstop.isa (11829:cb5390385d87)
1// Copyright (c) 2007-2008 The Hewlett-Packard Development Company
2// Copyright (c) 2015 Advanced Micro Devices, Inc.
3// All rights reserved.
4//
5// The license below extends only to copyright in the software and shall
6// not be construed as granting a license to any other intellectual
7// property including but not limited to intellectual property relating
8// to a hardware implementation of the functionality of the software

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310 {
311 %(constructor)s;
312 }
313}};
314
315let {{
316 class LdStOp(X86Microop):
317 def __init__(self, data, segment, addr, disp,
1// Copyright (c) 2007-2008 The Hewlett-Packard Development Company
2// Copyright (c) 2015 Advanced Micro Devices, Inc.
3// All rights reserved.
4//
5// The license below extends only to copyright in the software and shall
6// not be construed as granting a license to any other intellectual
7// property including but not limited to intellectual property relating
8// to a hardware implementation of the functionality of the software

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310 {
311 %(constructor)s;
312 }
313}};
314
315let {{
316 class LdStOp(X86Microop):
317 def __init__(self, data, segment, addr, disp,
318 dataSize, addressSize, baseFlags, atCPL0, prefetch, nonSpec):
318 dataSize, addressSize, baseFlags, atCPL0, prefetch, nonSpec,
319 implicitStack):
319 self.data = data
320 [self.scale, self.index, self.base] = addr
321 self.disp = disp
322 self.segment = segment
323 self.dataSize = dataSize
324 self.addressSize = addressSize
325 self.memFlags = baseFlags
326 if atCPL0:
327 self.memFlags += " | (CPL0FlagBit << FlagShift)"
328 self.instFlags = ""
329 if prefetch:
330 self.memFlags += " | Request::PREFETCH"
331 self.instFlags += " | (1ULL << StaticInst::IsDataPrefetch)"
332 if nonSpec:
333 self.instFlags += " | (1ULL << StaticInst::IsNonSpeculative)"
320 self.data = data
321 [self.scale, self.index, self.base] = addr
322 self.disp = disp
323 self.segment = segment
324 self.dataSize = dataSize
325 self.addressSize = addressSize
326 self.memFlags = baseFlags
327 if atCPL0:
328 self.memFlags += " | (CPL0FlagBit << FlagShift)"
329 self.instFlags = ""
330 if prefetch:
331 self.memFlags += " | Request::PREFETCH"
332 self.instFlags += " | (1ULL << StaticInst::IsDataPrefetch)"
333 if nonSpec:
334 self.instFlags += " | (1ULL << StaticInst::IsNonSpeculative)"
334 self.memFlags += " | (machInst.legacy.addr ? " + \
335 "(AddrSizeFlagBit << FlagShift) : 0)"
335 # For implicit stack operations, we should use *not* use the
336 # alternative addressing mode for loads/stores if the prefix is set
337 if not implicitStack:
338 self.memFlags += " | (machInst.legacy.addr ? " + \
339 "(AddrSizeFlagBit << FlagShift) : 0)"
336
337 def getAllocator(self, microFlags):
338 allocator = '''new %(class_name)s(machInst, macrocodeBlock,
339 %(flags)s, %(scale)s, %(index)s, %(base)s,
340 %(disp)s, %(segment)s, %(data)s,
341 %(dataSize)s, %(addressSize)s, %(memFlags)s)''' % {
342 "class_name" : self.className,
343 "flags" : self.microFlagsText(microFlags) + self.instFlags,
344 "scale" : self.scale, "index" : self.index,
345 "base" : self.base,
346 "disp" : self.disp,
347 "segment" : self.segment, "data" : self.data,
348 "dataSize" : self.dataSize, "addressSize" : self.addressSize,
349 "memFlags" : self.memFlags}
350 return allocator
351
352 class BigLdStOp(X86Microop):
353 def __init__(self, data, segment, addr, disp,
340
341 def getAllocator(self, microFlags):
342 allocator = '''new %(class_name)s(machInst, macrocodeBlock,
343 %(flags)s, %(scale)s, %(index)s, %(base)s,
344 %(disp)s, %(segment)s, %(data)s,
345 %(dataSize)s, %(addressSize)s, %(memFlags)s)''' % {
346 "class_name" : self.className,
347 "flags" : self.microFlagsText(microFlags) + self.instFlags,
348 "scale" : self.scale, "index" : self.index,
349 "base" : self.base,
350 "disp" : self.disp,
351 "segment" : self.segment, "data" : self.data,
352 "dataSize" : self.dataSize, "addressSize" : self.addressSize,
353 "memFlags" : self.memFlags}
354 return allocator
355
356 class BigLdStOp(X86Microop):
357 def __init__(self, data, segment, addr, disp,
354 dataSize, addressSize, baseFlags, atCPL0, prefetch, nonSpec):
358 dataSize, addressSize, baseFlags, atCPL0, prefetch, nonSpec,
359 implicitStack):
355 self.data = data
356 [self.scale, self.index, self.base] = addr
357 self.disp = disp
358 self.segment = segment
359 self.dataSize = dataSize
360 self.addressSize = addressSize
361 self.memFlags = baseFlags
362 if atCPL0:
363 self.memFlags += " | (CPL0FlagBit << FlagShift)"
364 self.instFlags = ""
365 if prefetch:
366 self.memFlags += " | Request::PREFETCH"
367 self.instFlags += " | (1ULL << StaticInst::IsDataPrefetch)"
368 if nonSpec:
369 self.instFlags += " | (1ULL << StaticInst::IsNonSpeculative)"
360 self.data = data
361 [self.scale, self.index, self.base] = addr
362 self.disp = disp
363 self.segment = segment
364 self.dataSize = dataSize
365 self.addressSize = addressSize
366 self.memFlags = baseFlags
367 if atCPL0:
368 self.memFlags += " | (CPL0FlagBit << FlagShift)"
369 self.instFlags = ""
370 if prefetch:
371 self.memFlags += " | Request::PREFETCH"
372 self.instFlags += " | (1ULL << StaticInst::IsDataPrefetch)"
373 if nonSpec:
374 self.instFlags += " | (1ULL << StaticInst::IsNonSpeculative)"
370 self.memFlags += " | (machInst.legacy.addr ? " + \
371 "(AddrSizeFlagBit << FlagShift) : 0)"
375 # For implicit stack operations, we should use *not* use the
376 # alternative addressing mode for loads/stores if the prefix is set
377 if not implicitStack:
378 self.memFlags += " | (machInst.legacy.addr ? " + \
379 "(AddrSizeFlagBit << FlagShift) : 0)"
372
373 def getAllocator(self, microFlags):
374 allocString = '''
375 (%(dataSize)s >= 4) ?
376 (StaticInstPtr)(new %(class_name)sBig(machInst,
377 macrocodeBlock, %(flags)s, %(scale)s, %(index)s,
378 %(base)s, %(disp)s, %(segment)s, %(data)s,
379 %(dataSize)s, %(addressSize)s, %(memFlags)s)) :

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390 "disp" : self.disp,
391 "segment" : self.segment, "data" : self.data,
392 "dataSize" : self.dataSize, "addressSize" : self.addressSize,
393 "memFlags" : self.memFlags}
394 return allocator
395
396 class LdStSplitOp(LdStOp):
397 def __init__(self, data, segment, addr, disp,
380
381 def getAllocator(self, microFlags):
382 allocString = '''
383 (%(dataSize)s >= 4) ?
384 (StaticInstPtr)(new %(class_name)sBig(machInst,
385 macrocodeBlock, %(flags)s, %(scale)s, %(index)s,
386 %(base)s, %(disp)s, %(segment)s, %(data)s,
387 %(dataSize)s, %(addressSize)s, %(memFlags)s)) :

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398 "disp" : self.disp,
399 "segment" : self.segment, "data" : self.data,
400 "dataSize" : self.dataSize, "addressSize" : self.addressSize,
401 "memFlags" : self.memFlags}
402 return allocator
403
404 class LdStSplitOp(LdStOp):
405 def __init__(self, data, segment, addr, disp,
398 dataSize, addressSize, baseFlags, atCPL0, prefetch, nonSpec):
406 dataSize, addressSize, baseFlags, atCPL0, prefetch, nonSpec,
407 implicitStack):
399 super(LdStSplitOp, self).__init__(0, segment, addr, disp,
408 super(LdStSplitOp, self).__init__(0, segment, addr, disp,
400 dataSize, addressSize, baseFlags, atCPL0, prefetch, nonSpec)
409 dataSize, addressSize, baseFlags, atCPL0, prefetch, nonSpec,
410 implicitStack)
401 (self.dataLow, self.dataHi) = data
402
403 def getAllocator(self, microFlags):
404 allocString = '''(StaticInstPtr)(new %(class_name)s(machInst,
405 macrocodeBlock, %(flags)s, %(scale)s, %(index)s,
406 %(base)s, %(disp)s, %(segment)s,
407 %(dataLow)s, %(dataHi)s,
408 %(dataSize)s, %(addressSize)s, %(memFlags)s))

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430 exec_output = ""
431
432 segmentEAExpr = \
433 'bits(scale * Index + Base + disp, addressSize * 8 - 1, 0);'
434
435 calculateEA = 'EA = SegBase + ' + segmentEAExpr
436
437 def defineMicroLoadOp(mnemonic, code, bigCode='',
411 (self.dataLow, self.dataHi) = data
412
413 def getAllocator(self, microFlags):
414 allocString = '''(StaticInstPtr)(new %(class_name)s(machInst,
415 macrocodeBlock, %(flags)s, %(scale)s, %(index)s,
416 %(base)s, %(disp)s, %(segment)s,
417 %(dataLow)s, %(dataHi)s,
418 %(dataSize)s, %(addressSize)s, %(memFlags)s))

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440 exec_output = ""
441
442 segmentEAExpr = \
443 'bits(scale * Index + Base + disp, addressSize * 8 - 1, 0);'
444
445 calculateEA = 'EA = SegBase + ' + segmentEAExpr
446
447 def defineMicroLoadOp(mnemonic, code, bigCode='',
438 mem_flags="0", big=True, nonSpec=False):
448 mem_flags="0", big=True, nonSpec=False,
449 implicitStack=False):
439 global header_output
440 global decoder_output
441 global exec_output
442 global microopClasses
443 Name = mnemonic
444 name = mnemonic.lower()
445
446 # Build up the all register version of this micro op

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455 "memDataSize": "dataSize" })]
456 for iop in iops:
457 header_output += MicroLdStOpDeclare.subst(iop)
458 decoder_output += MicroLdStOpConstructor.subst(iop)
459 exec_output += MicroLoadExecute.subst(iop)
460 exec_output += MicroLoadInitiateAcc.subst(iop)
461 exec_output += MicroLoadCompleteAcc.subst(iop)
462
450 global header_output
451 global decoder_output
452 global exec_output
453 global microopClasses
454 Name = mnemonic
455 name = mnemonic.lower()
456
457 # Build up the all register version of this micro op

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466 "memDataSize": "dataSize" })]
467 for iop in iops:
468 header_output += MicroLdStOpDeclare.subst(iop)
469 decoder_output += MicroLdStOpConstructor.subst(iop)
470 exec_output += MicroLoadExecute.subst(iop)
471 exec_output += MicroLoadInitiateAcc.subst(iop)
472 exec_output += MicroLoadCompleteAcc.subst(iop)
473
474 if implicitStack:
475 # For instructions that implicitly access the stack, the address
476 # size is the same as the stack segment pointer size, not the
477 # address size if specified by the instruction prefix
478 addressSize = "env.stackSize"
479 else:
480 addressSize = "env.addressSize"
481
463 base = LdStOp
464 if big:
465 base = BigLdStOp
466 class LoadOp(base):
467 def __init__(self, data, segment, addr, disp = 0,
468 dataSize="env.dataSize",
482 base = LdStOp
483 if big:
484 base = BigLdStOp
485 class LoadOp(base):
486 def __init__(self, data, segment, addr, disp = 0,
487 dataSize="env.dataSize",
469 addressSize="env.addressSize",
470 atCPL0=False, prefetch=False, nonSpec=nonSpec):
488 addressSize=addressSize,
489 atCPL0=False, prefetch=False, nonSpec=nonSpec,
490 implicitStack=implicitStack):
471 super(LoadOp, self).__init__(data, segment, addr,
472 disp, dataSize, addressSize, mem_flags,
491 super(LoadOp, self).__init__(data, segment, addr,
492 disp, dataSize, addressSize, mem_flags,
473 atCPL0, prefetch, nonSpec)
493 atCPL0, prefetch, nonSpec, implicitStack)
474 self.className = Name
475 self.mnemonic = name
476
477 microopClasses[name] = LoadOp
478
479 defineMicroLoadOp('Ld', 'Data = merge(Data, Mem, dataSize);',
480 'Data = Mem & mask(dataSize * 8);')
494 self.className = Name
495 self.mnemonic = name
496
497 microopClasses[name] = LoadOp
498
499 defineMicroLoadOp('Ld', 'Data = merge(Data, Mem, dataSize);',
500 'Data = Mem & mask(dataSize * 8);')
501 defineMicroLoadOp('Ldis', 'Data = merge(Data, Mem, dataSize);',
502 'Data = Mem & mask(dataSize * 8);',
503 implicitStack=True)
481 defineMicroLoadOp('Ldst', 'Data = merge(Data, Mem, dataSize);',
482 'Data = Mem & mask(dataSize * 8);',
483 '(StoreCheck << FlagShift)')
484 defineMicroLoadOp('Ldstl', 'Data = merge(Data, Mem, dataSize);',
485 'Data = Mem & mask(dataSize * 8);',
486 '(StoreCheck << FlagShift) | Request::LOCKED_RMW',
487 nonSpec=True)
488

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539 exec_output += MicroLoadExecute.subst(iop)
540 exec_output += MicroLoadInitiateAcc.subst(iop)
541 exec_output += MicroLoadCompleteAcc.subst(iop)
542
543 class LoadOp(LdStSplitOp):
544 def __init__(self, data, segment, addr, disp = 0,
545 dataSize="env.dataSize",
546 addressSize="env.addressSize",
504 defineMicroLoadOp('Ldst', 'Data = merge(Data, Mem, dataSize);',
505 'Data = Mem & mask(dataSize * 8);',
506 '(StoreCheck << FlagShift)')
507 defineMicroLoadOp('Ldstl', 'Data = merge(Data, Mem, dataSize);',
508 'Data = Mem & mask(dataSize * 8);',
509 '(StoreCheck << FlagShift) | Request::LOCKED_RMW',
510 nonSpec=True)
511

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562 exec_output += MicroLoadExecute.subst(iop)
563 exec_output += MicroLoadInitiateAcc.subst(iop)
564 exec_output += MicroLoadCompleteAcc.subst(iop)
565
566 class LoadOp(LdStSplitOp):
567 def __init__(self, data, segment, addr, disp = 0,
568 dataSize="env.dataSize",
569 addressSize="env.addressSize",
547 atCPL0=False, prefetch=False, nonSpec=nonSpec):
570 atCPL0=False, prefetch=False, nonSpec=nonSpec,
571 implicitStack=False):
548 super(LoadOp, self).__init__(data, segment, addr,
549 disp, dataSize, addressSize, mem_flags,
572 super(LoadOp, self).__init__(data, segment, addr,
573 disp, dataSize, addressSize, mem_flags,
550 atCPL0, prefetch, nonSpec)
574 atCPL0, prefetch, nonSpec, implicitStack)
551 self.className = Name
552 self.mnemonic = name
553
554 microopClasses[name] = LoadOp
555
556 code = '''
557 switch (dataSize) {
558 case 4:

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569
570 defineMicroLoadSplitOp('LdSplit', code,
571 '(StoreCheck << FlagShift)')
572
573 defineMicroLoadSplitOp('LdSplitl', code,
574 '(StoreCheck << FlagShift) | Request::LOCKED_RMW',
575 nonSpec=True)
576
575 self.className = Name
576 self.mnemonic = name
577
578 microopClasses[name] = LoadOp
579
580 code = '''
581 switch (dataSize) {
582 case 4:

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593
594 defineMicroLoadSplitOp('LdSplit', code,
595 '(StoreCheck << FlagShift)')
596
597 defineMicroLoadSplitOp('LdSplitl', code,
598 '(StoreCheck << FlagShift) | Request::LOCKED_RMW',
599 nonSpec=True)
600
577 def defineMicroStoreOp(mnemonic, code, completeCode="", mem_flags="0"):
601 def defineMicroStoreOp(mnemonic, code, completeCode="", mem_flags="0",
602 implicitStack=False):
578 global header_output
579 global decoder_output
580 global exec_output
581 global microopClasses
582 Name = mnemonic
583 name = mnemonic.lower()
584
585 # Build up the all register version of this micro op
586 iop = InstObjParams(name, Name, 'X86ISA::LdStOp',
587 { "code": code,
588 "complete_code": completeCode,
589 "ea_code": calculateEA,
590 "memDataSize": "dataSize" })
591 header_output += MicroLdStOpDeclare.subst(iop)
592 decoder_output += MicroLdStOpConstructor.subst(iop)
593 exec_output += MicroStoreExecute.subst(iop)
594 exec_output += MicroStoreInitiateAcc.subst(iop)
595 exec_output += MicroStoreCompleteAcc.subst(iop)
596
603 global header_output
604 global decoder_output
605 global exec_output
606 global microopClasses
607 Name = mnemonic
608 name = mnemonic.lower()
609
610 # Build up the all register version of this micro op
611 iop = InstObjParams(name, Name, 'X86ISA::LdStOp',
612 { "code": code,
613 "complete_code": completeCode,
614 "ea_code": calculateEA,
615 "memDataSize": "dataSize" })
616 header_output += MicroLdStOpDeclare.subst(iop)
617 decoder_output += MicroLdStOpConstructor.subst(iop)
618 exec_output += MicroStoreExecute.subst(iop)
619 exec_output += MicroStoreInitiateAcc.subst(iop)
620 exec_output += MicroStoreCompleteAcc.subst(iop)
621
622 if implicitStack:
623 # For instructions that implicitly access the stack, the address
624 # size is the same as the stack segment pointer size, not the
625 # address size if specified by the instruction prefix
626 addressSize = "env.stackSize"
627 else:
628 addressSize = "env.addressSize"
629
597 class StoreOp(LdStOp):
598 def __init__(self, data, segment, addr, disp = 0,
599 dataSize="env.dataSize",
630 class StoreOp(LdStOp):
631 def __init__(self, data, segment, addr, disp = 0,
632 dataSize="env.dataSize",
600 addressSize="env.addressSize",
601 atCPL0=False, nonSpec=False):
633 addressSize=addressSize,
634 atCPL0=False, nonSpec=False, implicitStack=implicitStack):
602 super(StoreOp, self).__init__(data, segment, addr, disp,
603 dataSize, addressSize, mem_flags, atCPL0, False,
635 super(StoreOp, self).__init__(data, segment, addr, disp,
636 dataSize, addressSize, mem_flags, atCPL0, False,
604 nonSpec)
637 nonSpec, implicitStack)
605 self.className = Name
606 self.mnemonic = name
607
608 microopClasses[name] = StoreOp
609
610 defineMicroStoreOp('St', 'Mem = pick(Data, 2, dataSize);')
638 self.className = Name
639 self.mnemonic = name
640
641 microopClasses[name] = StoreOp
642
643 defineMicroStoreOp('St', 'Mem = pick(Data, 2, dataSize);')
644 defineMicroStoreOp('Stis', 'Mem = pick(Data, 2, dataSize);',
645 implicitStack=True)
611 defineMicroStoreOp('Stul', 'Mem = pick(Data, 2, dataSize);',
612 mem_flags="Request::LOCKED_RMW")
613
614 defineMicroStoreOp('Stfp', code='Mem = FpData_uqw;')
615
616 defineMicroStoreOp('Stfp87', code='''
617 switch (dataSize)
618 {

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650 exec_output += MicroStoreExecute.subst(iop)
651 exec_output += MicroStoreInitiateAcc.subst(iop)
652 exec_output += MicroStoreCompleteAcc.subst(iop)
653
654 class StoreOp(LdStSplitOp):
655 def __init__(self, data, segment, addr, disp = 0,
656 dataSize="env.dataSize",
657 addressSize="env.addressSize",
646 defineMicroStoreOp('Stul', 'Mem = pick(Data, 2, dataSize);',
647 mem_flags="Request::LOCKED_RMW")
648
649 defineMicroStoreOp('Stfp', code='Mem = FpData_uqw;')
650
651 defineMicroStoreOp('Stfp87', code='''
652 switch (dataSize)
653 {

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685 exec_output += MicroStoreExecute.subst(iop)
686 exec_output += MicroStoreInitiateAcc.subst(iop)
687 exec_output += MicroStoreCompleteAcc.subst(iop)
688
689 class StoreOp(LdStSplitOp):
690 def __init__(self, data, segment, addr, disp = 0,
691 dataSize="env.dataSize",
692 addressSize="env.addressSize",
658 atCPL0=False, nonSpec=False):
693 atCPL0=False, nonSpec=False, implicitStack=False):
659 super(StoreOp, self).__init__(data, segment, addr, disp,
660 dataSize, addressSize, mem_flags, atCPL0, False,
694 super(StoreOp, self).__init__(data, segment, addr, disp,
695 dataSize, addressSize, mem_flags, atCPL0, False,
661 nonSpec)
696 nonSpec, implicitStack)
662 self.className = Name
663 self.mnemonic = name
664
665 microopClasses[name] = StoreOp
666
667 code = '''
668 switch (dataSize) {
669 case 4:

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689 header_output += MicroLeaDeclare.subst(iop)
690 decoder_output += MicroLdStOpConstructor.subst(iop)
691 exec_output += MicroLeaExecute.subst(iop)
692
693 class LeaOp(LdStOp):
694 def __init__(self, data, segment, addr, disp = 0,
695 dataSize="env.dataSize", addressSize="env.addressSize"):
696 super(LeaOp, self).__init__(data, segment, addr, disp,
697 self.className = Name
698 self.mnemonic = name
699
700 microopClasses[name] = StoreOp
701
702 code = '''
703 switch (dataSize) {
704 case 4:

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724 header_output += MicroLeaDeclare.subst(iop)
725 decoder_output += MicroLdStOpConstructor.subst(iop)
726 exec_output += MicroLeaExecute.subst(iop)
727
728 class LeaOp(LdStOp):
729 def __init__(self, data, segment, addr, disp = 0,
730 dataSize="env.dataSize", addressSize="env.addressSize"):
731 super(LeaOp, self).__init__(data, segment, addr, disp,
697 dataSize, addressSize, "0", False, False, False)
732 dataSize, addressSize, "0", False, False, False, False)
698 self.className = "Lea"
699 self.mnemonic = "lea"
700
701 microopClasses["lea"] = LeaOp
702
703
704 iop = InstObjParams("tia", "Tia", 'X86ISA::LdStOp',
705 { "code": "xc->demapPage(EA, 0);",

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710 exec_output += MicroLeaExecute.subst(iop)
711
712 class TiaOp(LdStOp):
713 def __init__(self, segment, addr, disp = 0,
714 dataSize="env.dataSize",
715 addressSize="env.addressSize"):
716 super(TiaOp, self).__init__("InstRegIndex(NUM_INTREGS)", segment,
717 addr, disp, dataSize, addressSize, "0", False, False,
733 self.className = "Lea"
734 self.mnemonic = "lea"
735
736 microopClasses["lea"] = LeaOp
737
738
739 iop = InstObjParams("tia", "Tia", 'X86ISA::LdStOp',
740 { "code": "xc->demapPage(EA, 0);",

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745 exec_output += MicroLeaExecute.subst(iop)
746
747 class TiaOp(LdStOp):
748 def __init__(self, segment, addr, disp = 0,
749 dataSize="env.dataSize",
750 addressSize="env.addressSize"):
751 super(TiaOp, self).__init__("InstRegIndex(NUM_INTREGS)", segment,
752 addr, disp, dataSize, addressSize, "0", False, False,
718 False)
753 False, False)
719 self.className = "Tia"
720 self.mnemonic = "tia"
721
722 microopClasses["tia"] = TiaOp
723
724 class CdaOp(LdStOp):
725 def __init__(self, segment, addr, disp = 0,
726 dataSize="env.dataSize",
727 addressSize="env.addressSize", atCPL0=False):
728 super(CdaOp, self).__init__("InstRegIndex(NUM_INTREGS)", segment,
729 addr, disp, dataSize, addressSize, "Request::NO_ACCESS",
754 self.className = "Tia"
755 self.mnemonic = "tia"
756
757 microopClasses["tia"] = TiaOp
758
759 class CdaOp(LdStOp):
760 def __init__(self, segment, addr, disp = 0,
761 dataSize="env.dataSize",
762 addressSize="env.addressSize", atCPL0=False):
763 super(CdaOp, self).__init__("InstRegIndex(NUM_INTREGS)", segment,
764 addr, disp, dataSize, addressSize, "Request::NO_ACCESS",
730 atCPL0, False, False)
765 atCPL0, False, False, False)
731 self.className = "Cda"
732 self.mnemonic = "cda"
733
734 microopClasses["cda"] = CdaOp
735}};
766 self.className = "Cda"
767 self.mnemonic = "cda"
768
769 microopClasses["cda"] = CdaOp
770}};
736