1a2
> // Copyright (c) 2015 Advanced Micro Devices, Inc.
101c102,103
< fault = readMemAtomic(xc, traceData, EA, Mem, dataSize, memFlags);
---
> fault = readMemAtomic(xc, traceData, EA, Mem,
> %(memDataSize)s, memFlags);
130c132,133
< fault = initiateMemRead(xc, traceData, EA, dataSize, memFlags);
---
> fault = initiateMemRead(xc, traceData, EA,
> %(memDataSize)s, memFlags);
146c149
< getMem(pkt, Mem, dataSize, traceData);
---
> getMem(pkt, Mem, %(memDataSize)s, traceData);
177c180
< fault = writeMemAtomic(xc, traceData, Mem, dataSize, EA,
---
> fault = writeMemAtomic(xc, traceData, Mem, %(memDataSize)s, EA,
205c208
< fault = writeMemTiming(xc, traceData, Mem, dataSize, EA,
---
> fault = writeMemTiming(xc, traceData, Mem, %(memDataSize)s, EA,
255a259,280
> // LdStSplitOp is a load or store that uses a pair of regs as the
> // source or destination. Used for cmpxchg{8,16}b.
> def template MicroLdStSplitOpDeclare {{
> class %(class_name)s : public %(base_class)s
> {
> public:
> %(class_name)s(ExtMachInst _machInst,
> const char * instMnem, uint64_t setFlags,
> uint8_t _scale, InstRegIndex _index, InstRegIndex _base,
> uint64_t _disp, InstRegIndex _segment,
> InstRegIndex _dataLow, InstRegIndex _dataHi,
> uint8_t _dataSize, uint8_t _addressSize,
> Request::FlagsType _memFlags);
>
> %(BasicExecDeclare)s
>
> %(InitiateAccDeclare)s
>
> %(CompleteAccDeclare)s
> };
> }};
>
272a298,314
> def template MicroLdStSplitOpConstructor {{
> %(class_name)s::%(class_name)s(
> ExtMachInst machInst, const char * instMnem, uint64_t setFlags,
> uint8_t _scale, InstRegIndex _index, InstRegIndex _base,
> uint64_t _disp, InstRegIndex _segment,
> InstRegIndex _dataLow, InstRegIndex _dataHi,
> uint8_t _dataSize, uint8_t _addressSize,
> Request::FlagsType _memFlags) :
> %(base_class)s(machInst, "%(mnemonic)s", instMnem, setFlags,
> _scale, _index, _base,
> _disp, _segment, _dataLow, _dataHi,
> _dataSize, _addressSize, _memFlags, %(op_class)s)
> {
> %(constructor)s;
> }
> }};
>
352a395,421
>
> class LdStSplitOp(LdStOp):
> def __init__(self, data, segment, addr, disp,
> dataSize, addressSize, baseFlags, atCPL0, prefetch, nonSpec):
> super(LdStSplitOp, self).__init__(0, segment, addr, disp,
> dataSize, addressSize, baseFlags, atCPL0, prefetch, nonSpec)
> (self.dataLow, self.dataHi) = data
>
> def getAllocator(self, microFlags):
> allocString = '''(StaticInstPtr)(new %(class_name)s(machInst,
> macrocodeBlock, %(flags)s, %(scale)s, %(index)s,
> %(base)s, %(disp)s, %(segment)s,
> %(dataLow)s, %(dataHi)s,
> %(dataSize)s, %(addressSize)s, %(memFlags)s))
> '''
> allocator = allocString % {
> "class_name" : self.className,
> "flags" : self.microFlagsText(microFlags) + self.instFlags,
> "scale" : self.scale, "index" : self.index,
> "base" : self.base,
> "disp" : self.disp,
> "segment" : self.segment,
> "dataLow" : self.dataLow, "dataHi" : self.dataHi,
> "dataSize" : self.dataSize, "addressSize" : self.addressSize,
> "memFlags" : self.memFlags}
> return allocator
>
363,365c432,433
< calculateEA = '''
< EA = SegBase + bits(scale * Index + Base + disp, addressSize * 8 - 1, 0);
< '''
---
> segmentEAExpr = \
> 'bits(scale * Index + Base + disp, addressSize * 8 - 1, 0);'
366a435,436
> calculateEA = 'EA = SegBase + ' + segmentEAExpr
>
368c438
< mem_flags="0", big=True):
---
> mem_flags="0", big=True, nonSpec=False):
378c448,450
< {"code": code, "ea_code": calculateEA})]
---
> { "code": code,
> "ea_code": calculateEA,
> "memDataSize": "dataSize" })]
381c453,455
< {"code": bigCode, "ea_code": calculateEA})]
---
> { "code": bigCode,
> "ea_code": calculateEA,
> "memDataSize": "dataSize" })]
396c470
< atCPL0=False, prefetch=False, nonSpec=False):
---
> atCPL0=False, prefetch=False, nonSpec=nonSpec):
412c486,487
< '(StoreCheck << FlagShift) | Request::LOCKED_RMW')
---
> '(StoreCheck << FlagShift) | Request::LOCKED_RMW',
> nonSpec=True)
448a524,576
> def defineMicroLoadSplitOp(mnemonic, code, mem_flags="0", nonSpec=False):
> global header_output
> global decoder_output
> global exec_output
> global microopClasses
> Name = mnemonic
> name = mnemonic.lower()
>
> iop = InstObjParams(name, Name, 'X86ISA::LdStSplitOp',
> { "code": code,
> "ea_code": calculateEA,
> "memDataSize": "2 * dataSize" })
>
> header_output += MicroLdStSplitOpDeclare.subst(iop)
> decoder_output += MicroLdStSplitOpConstructor.subst(iop)
> exec_output += MicroLoadExecute.subst(iop)
> exec_output += MicroLoadInitiateAcc.subst(iop)
> exec_output += MicroLoadCompleteAcc.subst(iop)
>
> class LoadOp(LdStSplitOp):
> def __init__(self, data, segment, addr, disp = 0,
> dataSize="env.dataSize",
> addressSize="env.addressSize",
> atCPL0=False, prefetch=False, nonSpec=nonSpec):
> super(LoadOp, self).__init__(data, segment, addr,
> disp, dataSize, addressSize, mem_flags,
> atCPL0, prefetch, nonSpec)
> self.className = Name
> self.mnemonic = name
>
> microopClasses[name] = LoadOp
>
> code = '''
> switch (dataSize) {
> case 4:
> DataLow = bits(Mem_u2qw[0], 31, 0);
> DataHi = bits(Mem_u2qw[0], 63, 32);
> break;
> case 8:
> DataLow = Mem_u2qw[0];
> DataHi = Mem_u2qw[1];
> break;
> default:
> panic("Unhandled data size %d in LdSplit.\\n", dataSize);
> }'''
>
> defineMicroLoadSplitOp('LdSplit', code,
> '(StoreCheck << FlagShift)')
>
> defineMicroLoadSplitOp('LdSplitl', code,
> '(StoreCheck << FlagShift) | Request::LOCKED_RMW',
> nonSpec=True)
>
459,461c587,590
< {"code": code,
< "complete_code": completeCode,
< "ea_code": calculateEA})
---
> { "code": code,
> "complete_code": completeCode,
> "ea_code": calculateEA,
> "memDataSize": "dataSize" })
503a633,684
> def defineMicroStoreSplitOp(mnemonic, code,
> completeCode="", mem_flags="0"):
> global header_output
> global decoder_output
> global exec_output
> global microopClasses
> Name = mnemonic
> name = mnemonic.lower()
>
> iop = InstObjParams(name, Name, 'X86ISA::LdStSplitOp',
> { "code": code,
> "complete_code": completeCode,
> "ea_code": calculateEA,
> "memDataSize": "2 * dataSize" })
>
> header_output += MicroLdStSplitOpDeclare.subst(iop)
> decoder_output += MicroLdStSplitOpConstructor.subst(iop)
> exec_output += MicroStoreExecute.subst(iop)
> exec_output += MicroStoreInitiateAcc.subst(iop)
> exec_output += MicroStoreCompleteAcc.subst(iop)
>
> class StoreOp(LdStSplitOp):
> def __init__(self, data, segment, addr, disp = 0,
> dataSize="env.dataSize",
> addressSize="env.addressSize",
> atCPL0=False, nonSpec=False):
> super(StoreOp, self).__init__(data, segment, addr, disp,
> dataSize, addressSize, mem_flags, atCPL0, False,
> nonSpec)
> self.className = Name
> self.mnemonic = name
>
> microopClasses[name] = StoreOp
>
> code = '''
> switch (dataSize) {
> case 4:
> Mem_u2qw[0] = (DataHi << 32) | DataLow;
> break;
> case 8:
> Mem_u2qw[0] = DataLow;
> Mem_u2qw[1] = DataHi;
> break;
> default:
> panic("Unhandled data size %d in StSplit.\\n", dataSize);
> }'''
>
> defineMicroStoreSplitOp('StSplit', code);
>
> defineMicroStoreSplitOp('StSplitul', code,
> mem_flags='Request::LOCKED_RMW')
>
505,508c686,688
< {"code": "Data = merge(Data, EA, dataSize);",
< "ea_code": '''
< EA = bits(scale * Index + Base + disp, addressSize * 8 - 1, 0);
< '''})
---
> { "code": "Data = merge(Data, EA, dataSize);",
> "ea_code": "EA = " + segmentEAExpr,
> "memDataSize": "dataSize" })
525,526c705,707
< {"code": "xc->demapPage(EA, 0);",
< "ea_code": calculateEA})
---
> { "code": "xc->demapPage(EA, 0);",
> "ea_code": calculateEA,
> "memDataSize": "dataSize" })
> // Copyright (c) 2015 Advanced Micro Devices, Inc.
101c102,103
< fault = readMemAtomic(xc, traceData, EA, Mem, dataSize, memFlags);
---
> fault = readMemAtomic(xc, traceData, EA, Mem,
> %(memDataSize)s, memFlags);
130c132,133
< fault = initiateMemRead(xc, traceData, EA, dataSize, memFlags);
---
> fault = initiateMemRead(xc, traceData, EA,
> %(memDataSize)s, memFlags);
146c149
< getMem(pkt, Mem, dataSize, traceData);
---
> getMem(pkt, Mem, %(memDataSize)s, traceData);
177c180
< fault = writeMemAtomic(xc, traceData, Mem, dataSize, EA,
---
> fault = writeMemAtomic(xc, traceData, Mem, %(memDataSize)s, EA,
205c208
< fault = writeMemTiming(xc, traceData, Mem, dataSize, EA,
---
> fault = writeMemTiming(xc, traceData, Mem, %(memDataSize)s, EA,
255a259,280
> // LdStSplitOp is a load or store that uses a pair of regs as the
> // source or destination. Used for cmpxchg{8,16}b.
> def template MicroLdStSplitOpDeclare {{
> class %(class_name)s : public %(base_class)s
> {
> public:
> %(class_name)s(ExtMachInst _machInst,
> const char * instMnem, uint64_t setFlags,
> uint8_t _scale, InstRegIndex _index, InstRegIndex _base,
> uint64_t _disp, InstRegIndex _segment,
> InstRegIndex _dataLow, InstRegIndex _dataHi,
> uint8_t _dataSize, uint8_t _addressSize,
> Request::FlagsType _memFlags);
>
> %(BasicExecDeclare)s
>
> %(InitiateAccDeclare)s
>
> %(CompleteAccDeclare)s
> };
> }};
>
272a298,314
> def template MicroLdStSplitOpConstructor {{
> %(class_name)s::%(class_name)s(
> ExtMachInst machInst, const char * instMnem, uint64_t setFlags,
> uint8_t _scale, InstRegIndex _index, InstRegIndex _base,
> uint64_t _disp, InstRegIndex _segment,
> InstRegIndex _dataLow, InstRegIndex _dataHi,
> uint8_t _dataSize, uint8_t _addressSize,
> Request::FlagsType _memFlags) :
> %(base_class)s(machInst, "%(mnemonic)s", instMnem, setFlags,
> _scale, _index, _base,
> _disp, _segment, _dataLow, _dataHi,
> _dataSize, _addressSize, _memFlags, %(op_class)s)
> {
> %(constructor)s;
> }
> }};
>
352a395,421
>
> class LdStSplitOp(LdStOp):
> def __init__(self, data, segment, addr, disp,
> dataSize, addressSize, baseFlags, atCPL0, prefetch, nonSpec):
> super(LdStSplitOp, self).__init__(0, segment, addr, disp,
> dataSize, addressSize, baseFlags, atCPL0, prefetch, nonSpec)
> (self.dataLow, self.dataHi) = data
>
> def getAllocator(self, microFlags):
> allocString = '''(StaticInstPtr)(new %(class_name)s(machInst,
> macrocodeBlock, %(flags)s, %(scale)s, %(index)s,
> %(base)s, %(disp)s, %(segment)s,
> %(dataLow)s, %(dataHi)s,
> %(dataSize)s, %(addressSize)s, %(memFlags)s))
> '''
> allocator = allocString % {
> "class_name" : self.className,
> "flags" : self.microFlagsText(microFlags) + self.instFlags,
> "scale" : self.scale, "index" : self.index,
> "base" : self.base,
> "disp" : self.disp,
> "segment" : self.segment,
> "dataLow" : self.dataLow, "dataHi" : self.dataHi,
> "dataSize" : self.dataSize, "addressSize" : self.addressSize,
> "memFlags" : self.memFlags}
> return allocator
>
363,365c432,433
< calculateEA = '''
< EA = SegBase + bits(scale * Index + Base + disp, addressSize * 8 - 1, 0);
< '''
---
> segmentEAExpr = \
> 'bits(scale * Index + Base + disp, addressSize * 8 - 1, 0);'
366a435,436
> calculateEA = 'EA = SegBase + ' + segmentEAExpr
>
368c438
< mem_flags="0", big=True):
---
> mem_flags="0", big=True, nonSpec=False):
378c448,450
< {"code": code, "ea_code": calculateEA})]
---
> { "code": code,
> "ea_code": calculateEA,
> "memDataSize": "dataSize" })]
381c453,455
< {"code": bigCode, "ea_code": calculateEA})]
---
> { "code": bigCode,
> "ea_code": calculateEA,
> "memDataSize": "dataSize" })]
396c470
< atCPL0=False, prefetch=False, nonSpec=False):
---
> atCPL0=False, prefetch=False, nonSpec=nonSpec):
412c486,487
< '(StoreCheck << FlagShift) | Request::LOCKED_RMW')
---
> '(StoreCheck << FlagShift) | Request::LOCKED_RMW',
> nonSpec=True)
448a524,576
> def defineMicroLoadSplitOp(mnemonic, code, mem_flags="0", nonSpec=False):
> global header_output
> global decoder_output
> global exec_output
> global microopClasses
> Name = mnemonic
> name = mnemonic.lower()
>
> iop = InstObjParams(name, Name, 'X86ISA::LdStSplitOp',
> { "code": code,
> "ea_code": calculateEA,
> "memDataSize": "2 * dataSize" })
>
> header_output += MicroLdStSplitOpDeclare.subst(iop)
> decoder_output += MicroLdStSplitOpConstructor.subst(iop)
> exec_output += MicroLoadExecute.subst(iop)
> exec_output += MicroLoadInitiateAcc.subst(iop)
> exec_output += MicroLoadCompleteAcc.subst(iop)
>
> class LoadOp(LdStSplitOp):
> def __init__(self, data, segment, addr, disp = 0,
> dataSize="env.dataSize",
> addressSize="env.addressSize",
> atCPL0=False, prefetch=False, nonSpec=nonSpec):
> super(LoadOp, self).__init__(data, segment, addr,
> disp, dataSize, addressSize, mem_flags,
> atCPL0, prefetch, nonSpec)
> self.className = Name
> self.mnemonic = name
>
> microopClasses[name] = LoadOp
>
> code = '''
> switch (dataSize) {
> case 4:
> DataLow = bits(Mem_u2qw[0], 31, 0);
> DataHi = bits(Mem_u2qw[0], 63, 32);
> break;
> case 8:
> DataLow = Mem_u2qw[0];
> DataHi = Mem_u2qw[1];
> break;
> default:
> panic("Unhandled data size %d in LdSplit.\\n", dataSize);
> }'''
>
> defineMicroLoadSplitOp('LdSplit', code,
> '(StoreCheck << FlagShift)')
>
> defineMicroLoadSplitOp('LdSplitl', code,
> '(StoreCheck << FlagShift) | Request::LOCKED_RMW',
> nonSpec=True)
>
459,461c587,590
< {"code": code,
< "complete_code": completeCode,
< "ea_code": calculateEA})
---
> { "code": code,
> "complete_code": completeCode,
> "ea_code": calculateEA,
> "memDataSize": "dataSize" })
503a633,684
> def defineMicroStoreSplitOp(mnemonic, code,
> completeCode="", mem_flags="0"):
> global header_output
> global decoder_output
> global exec_output
> global microopClasses
> Name = mnemonic
> name = mnemonic.lower()
>
> iop = InstObjParams(name, Name, 'X86ISA::LdStSplitOp',
> { "code": code,
> "complete_code": completeCode,
> "ea_code": calculateEA,
> "memDataSize": "2 * dataSize" })
>
> header_output += MicroLdStSplitOpDeclare.subst(iop)
> decoder_output += MicroLdStSplitOpConstructor.subst(iop)
> exec_output += MicroStoreExecute.subst(iop)
> exec_output += MicroStoreInitiateAcc.subst(iop)
> exec_output += MicroStoreCompleteAcc.subst(iop)
>
> class StoreOp(LdStSplitOp):
> def __init__(self, data, segment, addr, disp = 0,
> dataSize="env.dataSize",
> addressSize="env.addressSize",
> atCPL0=False, nonSpec=False):
> super(StoreOp, self).__init__(data, segment, addr, disp,
> dataSize, addressSize, mem_flags, atCPL0, False,
> nonSpec)
> self.className = Name
> self.mnemonic = name
>
> microopClasses[name] = StoreOp
>
> code = '''
> switch (dataSize) {
> case 4:
> Mem_u2qw[0] = (DataHi << 32) | DataLow;
> break;
> case 8:
> Mem_u2qw[0] = DataLow;
> Mem_u2qw[1] = DataHi;
> break;
> default:
> panic("Unhandled data size %d in StSplit.\\n", dataSize);
> }'''
>
> defineMicroStoreSplitOp('StSplit', code);
>
> defineMicroStoreSplitOp('StSplitul', code,
> mem_flags='Request::LOCKED_RMW')
>
505,508c686,688
< {"code": "Data = merge(Data, EA, dataSize);",
< "ea_code": '''
< EA = bits(scale * Index + Base + disp, addressSize * 8 - 1, 0);
< '''})
---
> { "code": "Data = merge(Data, EA, dataSize);",
> "ea_code": "EA = " + segmentEAExpr,
> "memDataSize": "dataSize" })
525,526c705,707
< {"code": "xc->demapPage(EA, 0);",
< "ea_code": calculateEA})
---
> { "code": "xc->demapPage(EA, 0);",
> "ea_code": calculateEA,
> "memDataSize": "dataSize" })