94 %(BasicExecDeclare)s 95 }; 96}}; 97 98// Load templates 99 100def template MicroLoadExecute {{ 101 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 102 Trace::InstRecord *traceData) const 103 { 104 Fault fault = NoFault; 105 Addr EA; 106 107 %(op_decl)s; 108 %(op_rd)s; 109 %(ea_code)s; 110 DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA); 111 112 fault = read(xc, EA, Mem, memFlags); 113 114 if (fault == NoFault) { 115 %(code)s; 116 } else if (memFlags & Request::PREFETCH) { 117 // For prefetches, ignore any faults/exceptions. 118 return NoFault; 119 } 120 if(fault == NoFault) 121 { 122 %(op_wb)s; 123 } 124 125 return fault; 126 } 127}}; 128 129def template MicroLoadInitiateAcc {{ 130 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s * xc, 131 Trace::InstRecord * traceData) const 132 { 133 Fault fault = NoFault; 134 Addr EA; 135 136 %(op_decl)s; 137 %(op_rd)s; 138 %(ea_code)s; 139 DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA); 140 141 fault = read(xc, EA, Mem, memFlags); 142 143 return fault; 144 } 145}}; 146 147def template MicroLoadCompleteAcc {{ 148 Fault %(class_name)s::completeAcc(PacketPtr pkt, 149 %(CPU_exec_context)s * xc, 150 Trace::InstRecord * traceData) const 151 { 152 Fault fault = NoFault; 153 154 %(op_decl)s; 155 %(op_rd)s; 156 157 Mem = get(pkt); 158 159 %(code)s; 160 161 if(fault == NoFault) 162 { 163 %(op_wb)s; 164 } 165 166 return fault; 167 } 168}}; 169 170// Store templates 171 172def template MicroStoreExecute {{ 173 Fault %(class_name)s::execute(%(CPU_exec_context)s * xc, 174 Trace::InstRecord *traceData) const 175 { 176 Fault fault = NoFault; 177 178 Addr EA; 179 %(op_decl)s; 180 %(op_rd)s; 181 %(ea_code)s; 182 DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA); 183 184 %(code)s; 185 186 if(fault == NoFault) 187 { 188 fault = write(xc, Mem, EA, memFlags); 189 if(fault == NoFault) 190 { 191 %(post_code)s; 192 %(op_wb)s; 193 } 194 } 195 196 return fault; 197 } 198}}; 199 200def template MicroStoreInitiateAcc {{ 201 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s * xc, 202 Trace::InstRecord * traceData) const 203 { 204 Fault fault = NoFault; 205 206 Addr EA; 207 %(op_decl)s; 208 %(op_rd)s; 209 %(ea_code)s; 210 DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA); 211 212 %(code)s; 213 214 if(fault == NoFault) 215 { 216 write(xc, Mem, EA, memFlags); 217 } 218 return fault; 219 } 220}}; 221 222def template MicroStoreCompleteAcc {{ 223 Fault %(class_name)s::completeAcc(PacketPtr pkt, 224 %(CPU_exec_context)s * xc, Trace::InstRecord * traceData) const 225 { 226 %(op_decl)s; 227 %(op_rd)s; 228 %(complete_code)s; 229 %(op_wb)s; 230 return NoFault; 231 } 232}}; 233 234// Common templates 235 236//This delcares the initiateAcc function in memory operations 237def template InitiateAccDeclare {{ 238 Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; 239}}; 240 241//This declares the completeAcc function in memory operations 242def template CompleteAccDeclare {{ 243 Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const; 244}}; 245 246def template MicroLdStOpDeclare {{ 247 class %(class_name)s : public %(base_class)s 248 {
| 83 %(BasicExecDeclare)s 84 }; 85}}; 86 87// Load templates 88 89def template MicroLoadExecute {{ 90 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 91 Trace::InstRecord *traceData) const 92 { 93 Fault fault = NoFault; 94 Addr EA; 95 96 %(op_decl)s; 97 %(op_rd)s; 98 %(ea_code)s; 99 DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA); 100 101 fault = read(xc, EA, Mem, memFlags); 102 103 if (fault == NoFault) { 104 %(code)s; 105 } else if (memFlags & Request::PREFETCH) { 106 // For prefetches, ignore any faults/exceptions. 107 return NoFault; 108 } 109 if(fault == NoFault) 110 { 111 %(op_wb)s; 112 } 113 114 return fault; 115 } 116}}; 117 118def template MicroLoadInitiateAcc {{ 119 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s * xc, 120 Trace::InstRecord * traceData) const 121 { 122 Fault fault = NoFault; 123 Addr EA; 124 125 %(op_decl)s; 126 %(op_rd)s; 127 %(ea_code)s; 128 DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA); 129 130 fault = read(xc, EA, Mem, memFlags); 131 132 return fault; 133 } 134}}; 135 136def template MicroLoadCompleteAcc {{ 137 Fault %(class_name)s::completeAcc(PacketPtr pkt, 138 %(CPU_exec_context)s * xc, 139 Trace::InstRecord * traceData) const 140 { 141 Fault fault = NoFault; 142 143 %(op_decl)s; 144 %(op_rd)s; 145 146 Mem = get(pkt); 147 148 %(code)s; 149 150 if(fault == NoFault) 151 { 152 %(op_wb)s; 153 } 154 155 return fault; 156 } 157}}; 158 159// Store templates 160 161def template MicroStoreExecute {{ 162 Fault %(class_name)s::execute(%(CPU_exec_context)s * xc, 163 Trace::InstRecord *traceData) const 164 { 165 Fault fault = NoFault; 166 167 Addr EA; 168 %(op_decl)s; 169 %(op_rd)s; 170 %(ea_code)s; 171 DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA); 172 173 %(code)s; 174 175 if(fault == NoFault) 176 { 177 fault = write(xc, Mem, EA, memFlags); 178 if(fault == NoFault) 179 { 180 %(post_code)s; 181 %(op_wb)s; 182 } 183 } 184 185 return fault; 186 } 187}}; 188 189def template MicroStoreInitiateAcc {{ 190 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s * xc, 191 Trace::InstRecord * traceData) const 192 { 193 Fault fault = NoFault; 194 195 Addr EA; 196 %(op_decl)s; 197 %(op_rd)s; 198 %(ea_code)s; 199 DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA); 200 201 %(code)s; 202 203 if(fault == NoFault) 204 { 205 write(xc, Mem, EA, memFlags); 206 } 207 return fault; 208 } 209}}; 210 211def template MicroStoreCompleteAcc {{ 212 Fault %(class_name)s::completeAcc(PacketPtr pkt, 213 %(CPU_exec_context)s * xc, Trace::InstRecord * traceData) const 214 { 215 %(op_decl)s; 216 %(op_rd)s; 217 %(complete_code)s; 218 %(op_wb)s; 219 return NoFault; 220 } 221}}; 222 223// Common templates 224 225//This delcares the initiateAcc function in memory operations 226def template InitiateAccDeclare {{ 227 Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; 228}}; 229 230//This declares the completeAcc function in memory operations 231def template CompleteAccDeclare {{ 232 Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const; 233}}; 234 235def template MicroLdStOpDeclare {{ 236 class %(class_name)s : public %(base_class)s 237 {
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312 } 313}}; 314 315let {{ 316 class LdStOp(X86Microop): 317 def __init__(self, data, segment, addr, disp, 318 dataSize, addressSize, baseFlags, atCPL0, prefetch): 319 self.data = data 320 [self.scale, self.index, self.base] = addr 321 self.disp = disp 322 self.segment = segment 323 self.dataSize = dataSize 324 self.addressSize = addressSize 325 self.memFlags = baseFlags 326 if atCPL0: 327 self.memFlags += " | (CPL0FlagBit << FlagShift)" 328 if prefetch: 329 self.memFlags += " | Request::PREFETCH" 330 self.memFlags += " | (machInst.legacy.addr ? " + \ 331 "(AddrSizeFlagBit << FlagShift) : 0)" 332 333 def getAllocator(self, microFlags): 334 allocator = '''new %(class_name)s(machInst, macrocodeBlock, 335 %(flags)s, %(scale)s, %(index)s, %(base)s, 336 %(disp)s, %(segment)s, %(data)s, 337 %(dataSize)s, %(addressSize)s, %(memFlags)s)''' % { 338 "class_name" : self.className, 339 "flags" : self.microFlagsText(microFlags), 340 "scale" : self.scale, "index" : self.index, 341 "base" : self.base, 342 "disp" : self.disp, 343 "segment" : self.segment, "data" : self.data, 344 "dataSize" : self.dataSize, "addressSize" : self.addressSize, 345 "memFlags" : self.memFlags} 346 return allocator 347}}; 348 349let {{ 350 351 # Make these empty strings so that concatenating onto 352 # them will always work. 353 header_output = "" 354 decoder_output = "" 355 exec_output = "" 356 357 calculateEA = ''' 358 EA = bits(SegBase + scale * Index + Base + disp, addressSize * 8 - 1, 0); 359 ''' 360 361 def defineMicroLoadOp(mnemonic, code, mem_flags="0"): 362 global header_output 363 global decoder_output 364 global exec_output 365 global microopClasses 366 Name = mnemonic 367 name = mnemonic.lower() 368 369 # Build up the all register version of this micro op 370 iop = InstObjParams(name, Name, 'X86ISA::LdStOp', 371 {"code": code, 372 "ea_code": calculateEA}) 373 header_output += MicroLdStOpDeclare.subst(iop) 374 decoder_output += MicroLdStOpConstructor.subst(iop) 375 exec_output += MicroLoadExecute.subst(iop) 376 exec_output += MicroLoadInitiateAcc.subst(iop) 377 exec_output += MicroLoadCompleteAcc.subst(iop) 378 379 class LoadOp(LdStOp): 380 def __init__(self, data, segment, addr, disp = 0, 381 dataSize="env.dataSize", 382 addressSize="env.addressSize", 383 atCPL0=False, prefetch=False): 384 super(LoadOp, self).__init__(data, segment, addr, 385 disp, dataSize, addressSize, mem_flags, 386 atCPL0, prefetch) 387 self.className = Name 388 self.mnemonic = name 389 390 microopClasses[name] = LoadOp 391 392 defineMicroLoadOp('Ld', 'Data = merge(Data, Mem, dataSize);') 393 defineMicroLoadOp('Ldst', 'Data = merge(Data, Mem, dataSize);', 394 '(StoreCheck << FlagShift)') 395 defineMicroLoadOp('Ldstl', 'Data = merge(Data, Mem, dataSize);', 396 '(StoreCheck << FlagShift) | Request::LOCKED') 397 defineMicroLoadOp('Ldfp', 'FpData.uqw = Mem;') 398 399 def defineMicroStoreOp(mnemonic, code, \ 400 postCode="", completeCode="", mem_flags="0"): 401 global header_output 402 global decoder_output 403 global exec_output 404 global microopClasses 405 Name = mnemonic 406 name = mnemonic.lower() 407 408 # Build up the all register version of this micro op 409 iop = InstObjParams(name, Name, 'X86ISA::LdStOp', 410 {"code": code, 411 "post_code": postCode, 412 "complete_code": completeCode, 413 "ea_code": calculateEA}) 414 header_output += MicroLdStOpDeclare.subst(iop) 415 decoder_output += MicroLdStOpConstructor.subst(iop) 416 exec_output += MicroStoreExecute.subst(iop) 417 exec_output += MicroStoreInitiateAcc.subst(iop) 418 exec_output += MicroStoreCompleteAcc.subst(iop) 419 420 class StoreOp(LdStOp): 421 def __init__(self, data, segment, addr, disp = 0, 422 dataSize="env.dataSize", 423 addressSize="env.addressSize", 424 atCPL0=False): 425 super(StoreOp, self).__init__(data, segment, addr, 426 disp, dataSize, addressSize, mem_flags, atCPL0, False) 427 self.className = Name 428 self.mnemonic = name 429 430 microopClasses[name] = StoreOp 431 432 defineMicroStoreOp('St', 'Mem = pick(Data, 2, dataSize);') 433 defineMicroStoreOp('Stul', 'Mem = pick(Data, 2, dataSize);', 434 mem_flags="Request::LOCKED") 435 defineMicroStoreOp('Stfp', 'Mem = FpData.uqw;') 436 defineMicroStoreOp('Stupd', 'Mem = pick(Data, 2, dataSize);', 437 'Base = merge(Base, EA - SegBase, addressSize);', 438 'Base = merge(Base, pkt->req->getVaddr() - SegBase, addressSize);'); 439 defineMicroStoreOp('Cda', 'Mem = 0;', mem_flags="Request::NO_ACCESS") 440 441 iop = InstObjParams("lea", "Lea", 'X86ISA::LdStOp', 442 {"code": "Data = merge(Data, EA, dataSize);", 443 "ea_code": ''' 444 EA = bits(scale * Index + Base + disp, addressSize * 8 - 1, 0); 445 '''}) 446 header_output += MicroLeaDeclare.subst(iop) 447 decoder_output += MicroLdStOpConstructor.subst(iop) 448 exec_output += MicroLeaExecute.subst(iop) 449 450 class LeaOp(LdStOp): 451 def __init__(self, data, segment, addr, disp = 0, 452 dataSize="env.dataSize", addressSize="env.addressSize"): 453 super(LeaOp, self).__init__(data, segment, 454 addr, disp, dataSize, addressSize, "0", False, False) 455 self.className = "Lea" 456 self.mnemonic = "lea" 457 458 microopClasses["lea"] = LeaOp 459 460 461 iop = InstObjParams("tia", "Tia", 'X86ISA::LdStOp', 462 {"code": "xc->demapPage(EA, 0);", 463 "ea_code": calculateEA}) 464 header_output += MicroLeaDeclare.subst(iop) 465 decoder_output += MicroLdStOpConstructor.subst(iop) 466 exec_output += MicroLeaExecute.subst(iop) 467 468 class TiaOp(LdStOp): 469 def __init__(self, segment, addr, disp = 0, 470 dataSize="env.dataSize", 471 addressSize="env.addressSize"): 472 super(TiaOp, self).__init__("InstRegIndex(NUM_INTREGS)", segment, 473 addr, disp, dataSize, addressSize, "0", False, False) 474 self.className = "Tia" 475 self.mnemonic = "tia" 476 477 microopClasses["tia"] = TiaOp 478 479 class CdaOp(LdStOp): 480 def __init__(self, segment, addr, disp = 0, 481 dataSize="env.dataSize", 482 addressSize="env.addressSize", atCPL0=False): 483 super(CdaOp, self).__init__("InstRegIndex(NUM_INTREGS)", segment, 484 addr, disp, dataSize, addressSize, "Request::NO_ACCESS", 485 atCPL0, False) 486 self.className = "Cda" 487 self.mnemonic = "cda" 488 489 microopClasses["cda"] = CdaOp 490}}; 491
| 269 } 270}}; 271 272let {{ 273 class LdStOp(X86Microop): 274 def __init__(self, data, segment, addr, disp, 275 dataSize, addressSize, baseFlags, atCPL0, prefetch): 276 self.data = data 277 [self.scale, self.index, self.base] = addr 278 self.disp = disp 279 self.segment = segment 280 self.dataSize = dataSize 281 self.addressSize = addressSize 282 self.memFlags = baseFlags 283 if atCPL0: 284 self.memFlags += " | (CPL0FlagBit << FlagShift)" 285 if prefetch: 286 self.memFlags += " | Request::PREFETCH" 287 self.memFlags += " | (machInst.legacy.addr ? " + \ 288 "(AddrSizeFlagBit << FlagShift) : 0)" 289 290 def getAllocator(self, microFlags): 291 allocator = '''new %(class_name)s(machInst, macrocodeBlock, 292 %(flags)s, %(scale)s, %(index)s, %(base)s, 293 %(disp)s, %(segment)s, %(data)s, 294 %(dataSize)s, %(addressSize)s, %(memFlags)s)''' % { 295 "class_name" : self.className, 296 "flags" : self.microFlagsText(microFlags), 297 "scale" : self.scale, "index" : self.index, 298 "base" : self.base, 299 "disp" : self.disp, 300 "segment" : self.segment, "data" : self.data, 301 "dataSize" : self.dataSize, "addressSize" : self.addressSize, 302 "memFlags" : self.memFlags} 303 return allocator 304}}; 305 306let {{ 307 308 # Make these empty strings so that concatenating onto 309 # them will always work. 310 header_output = "" 311 decoder_output = "" 312 exec_output = "" 313 314 calculateEA = ''' 315 EA = bits(SegBase + scale * Index + Base + disp, addressSize * 8 - 1, 0); 316 ''' 317 318 def defineMicroLoadOp(mnemonic, code, mem_flags="0"): 319 global header_output 320 global decoder_output 321 global exec_output 322 global microopClasses 323 Name = mnemonic 324 name = mnemonic.lower() 325 326 # Build up the all register version of this micro op 327 iop = InstObjParams(name, Name, 'X86ISA::LdStOp', 328 {"code": code, 329 "ea_code": calculateEA}) 330 header_output += MicroLdStOpDeclare.subst(iop) 331 decoder_output += MicroLdStOpConstructor.subst(iop) 332 exec_output += MicroLoadExecute.subst(iop) 333 exec_output += MicroLoadInitiateAcc.subst(iop) 334 exec_output += MicroLoadCompleteAcc.subst(iop) 335 336 class LoadOp(LdStOp): 337 def __init__(self, data, segment, addr, disp = 0, 338 dataSize="env.dataSize", 339 addressSize="env.addressSize", 340 atCPL0=False, prefetch=False): 341 super(LoadOp, self).__init__(data, segment, addr, 342 disp, dataSize, addressSize, mem_flags, 343 atCPL0, prefetch) 344 self.className = Name 345 self.mnemonic = name 346 347 microopClasses[name] = LoadOp 348 349 defineMicroLoadOp('Ld', 'Data = merge(Data, Mem, dataSize);') 350 defineMicroLoadOp('Ldst', 'Data = merge(Data, Mem, dataSize);', 351 '(StoreCheck << FlagShift)') 352 defineMicroLoadOp('Ldstl', 'Data = merge(Data, Mem, dataSize);', 353 '(StoreCheck << FlagShift) | Request::LOCKED') 354 defineMicroLoadOp('Ldfp', 'FpData.uqw = Mem;') 355 356 def defineMicroStoreOp(mnemonic, code, \ 357 postCode="", completeCode="", mem_flags="0"): 358 global header_output 359 global decoder_output 360 global exec_output 361 global microopClasses 362 Name = mnemonic 363 name = mnemonic.lower() 364 365 # Build up the all register version of this micro op 366 iop = InstObjParams(name, Name, 'X86ISA::LdStOp', 367 {"code": code, 368 "post_code": postCode, 369 "complete_code": completeCode, 370 "ea_code": calculateEA}) 371 header_output += MicroLdStOpDeclare.subst(iop) 372 decoder_output += MicroLdStOpConstructor.subst(iop) 373 exec_output += MicroStoreExecute.subst(iop) 374 exec_output += MicroStoreInitiateAcc.subst(iop) 375 exec_output += MicroStoreCompleteAcc.subst(iop) 376 377 class StoreOp(LdStOp): 378 def __init__(self, data, segment, addr, disp = 0, 379 dataSize="env.dataSize", 380 addressSize="env.addressSize", 381 atCPL0=False): 382 super(StoreOp, self).__init__(data, segment, addr, 383 disp, dataSize, addressSize, mem_flags, atCPL0, False) 384 self.className = Name 385 self.mnemonic = name 386 387 microopClasses[name] = StoreOp 388 389 defineMicroStoreOp('St', 'Mem = pick(Data, 2, dataSize);') 390 defineMicroStoreOp('Stul', 'Mem = pick(Data, 2, dataSize);', 391 mem_flags="Request::LOCKED") 392 defineMicroStoreOp('Stfp', 'Mem = FpData.uqw;') 393 defineMicroStoreOp('Stupd', 'Mem = pick(Data, 2, dataSize);', 394 'Base = merge(Base, EA - SegBase, addressSize);', 395 'Base = merge(Base, pkt->req->getVaddr() - SegBase, addressSize);'); 396 defineMicroStoreOp('Cda', 'Mem = 0;', mem_flags="Request::NO_ACCESS") 397 398 iop = InstObjParams("lea", "Lea", 'X86ISA::LdStOp', 399 {"code": "Data = merge(Data, EA, dataSize);", 400 "ea_code": ''' 401 EA = bits(scale * Index + Base + disp, addressSize * 8 - 1, 0); 402 '''}) 403 header_output += MicroLeaDeclare.subst(iop) 404 decoder_output += MicroLdStOpConstructor.subst(iop) 405 exec_output += MicroLeaExecute.subst(iop) 406 407 class LeaOp(LdStOp): 408 def __init__(self, data, segment, addr, disp = 0, 409 dataSize="env.dataSize", addressSize="env.addressSize"): 410 super(LeaOp, self).__init__(data, segment, 411 addr, disp, dataSize, addressSize, "0", False, False) 412 self.className = "Lea" 413 self.mnemonic = "lea" 414 415 microopClasses["lea"] = LeaOp 416 417 418 iop = InstObjParams("tia", "Tia", 'X86ISA::LdStOp', 419 {"code": "xc->demapPage(EA, 0);", 420 "ea_code": calculateEA}) 421 header_output += MicroLeaDeclare.subst(iop) 422 decoder_output += MicroLdStOpConstructor.subst(iop) 423 exec_output += MicroLeaExecute.subst(iop) 424 425 class TiaOp(LdStOp): 426 def __init__(self, segment, addr, disp = 0, 427 dataSize="env.dataSize", 428 addressSize="env.addressSize"): 429 super(TiaOp, self).__init__("InstRegIndex(NUM_INTREGS)", segment, 430 addr, disp, dataSize, addressSize, "0", False, False) 431 self.className = "Tia" 432 self.mnemonic = "tia" 433 434 microopClasses["tia"] = TiaOp 435 436 class CdaOp(LdStOp): 437 def __init__(self, segment, addr, disp = 0, 438 dataSize="env.dataSize", 439 addressSize="env.addressSize", atCPL0=False): 440 super(CdaOp, self).__init__("InstRegIndex(NUM_INTREGS)", segment, 441 addr, disp, dataSize, addressSize, "Request::NO_ACCESS", 442 atCPL0, False) 443 self.className = "Cda" 444 self.mnemonic = "cda" 445 446 microopClasses["cda"] = CdaOp 447}}; 448
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