1// Copyright (c) 2008 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

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119
120 public:
121 %(class_name)s(ExtMachInst _machInst,
122 const char * instMnem,
123 bool isMicro, bool isDelayed, bool isFirst, bool isLast,
124 uint8_t _scale, RegIndex _index, RegIndex _base,
125 uint64_t _disp, uint8_t _segment,
126 RegIndex _data,
127 uint8_t _dataSize, uint8_t _addressSize);
128
129 %(class_name)s(ExtMachInst _machInst,
130 const char * instMnem,
131 uint8_t _scale, RegIndex _index, RegIndex _base,
132 uint64_t _disp, uint8_t _segment,
133 RegIndex _data,
134 uint8_t _dataSize, uint8_t _addressSize);
135
136 %(BasicExecDeclare)s
137 };
138}};
139
140// Load templates
141
142def template MicroLoadExecute {{
143 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
144 Trace::InstRecord *traceData) const
145 {
146 Fault fault = NoFault;
147 Addr EA;
148
149 %(op_decl)s;
150 %(op_rd)s;
151 %(ea_code)s;
152 DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
153
154 fault = read(xc, EA, Mem, (%(mem_flags)s) | segment);
155
156 if(fault == NoFault)
157 {
158 %(code)s;
159 }
160 if(fault == NoFault)
161 {
162 %(op_wb)s;

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173 Fault fault = NoFault;
174 Addr EA;
175
176 %(op_decl)s;
177 %(op_rd)s;
178 %(ea_code)s;
179 DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
180
181 fault = read(xc, EA, Mem, (%(mem_flags)s) | segment);
182
183 return fault;
184 }
185}};
186
187def template MicroLoadCompleteAcc {{
188 Fault %(class_name)s::completeAcc(PacketPtr pkt,
189 %(CPU_exec_context)s * xc,

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220 %(op_rd)s;
221 %(ea_code)s;
222 DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
223
224 %(code)s;
225
226 if(fault == NoFault)
227 {
228 fault = write(xc, Mem, EA, (%(mem_flags)s) | segment);
229 if(fault == NoFault)
230 {
231 %(post_code)s;
232 %(op_wb)s;
233 }
234 }
235
236 return fault;

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248 %(op_rd)s;
249 %(ea_code)s;
250 DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
251
252 %(code)s;
253
254 if(fault == NoFault)
255 {
256 write(xc, Mem, EA, (%(mem_flags)s) | segment);
257 }
258 return fault;
259 }
260}};
261
262def template MicroStoreCompleteAcc {{
263 Fault %(class_name)s::completeAcc(PacketPtr pkt,
264 %(CPU_exec_context)s * xc, Trace::InstRecord * traceData) const

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291
292 public:
293 %(class_name)s(ExtMachInst _machInst,
294 const char * instMnem,
295 bool isMicro, bool isDelayed, bool isFirst, bool isLast,
296 uint8_t _scale, RegIndex _index, RegIndex _base,
297 uint64_t _disp, uint8_t _segment,
298 RegIndex _data,
299 uint8_t _dataSize, uint8_t _addressSize);
300
301 %(class_name)s(ExtMachInst _machInst,
302 const char * instMnem,
303 uint8_t _scale, RegIndex _index, RegIndex _base,
304 uint64_t _disp, uint8_t _segment,
305 RegIndex _data,
306 uint8_t _dataSize, uint8_t _addressSize);
307
308 %(BasicExecDeclare)s
309
310 %(InitiateAccDeclare)s
311
312 %(CompleteAccDeclare)s
313 };
314}};

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320 %(constructor)s;
321 }
322
323 inline %(class_name)s::%(class_name)s(
324 ExtMachInst machInst, const char * instMnem,
325 uint8_t _scale, RegIndex _index, RegIndex _base,
326 uint64_t _disp, uint8_t _segment,
327 RegIndex _data,
328 uint8_t _dataSize, uint8_t _addressSize) :
329 %(base_class)s(machInst, "%(mnemonic)s", instMnem,
330 false, false, false, false,
331 _scale, _index, _base,
332 _disp, _segment, _data,
333 _dataSize, _addressSize, %(op_class)s)
334 {
335 buildMe();
336 }
337
338 inline %(class_name)s::%(class_name)s(
339 ExtMachInst machInst, const char * instMnem,
340 bool isMicro, bool isDelayed, bool isFirst, bool isLast,
341 uint8_t _scale, RegIndex _index, RegIndex _base,
342 uint64_t _disp, uint8_t _segment,
343 RegIndex _data,
344 uint8_t _dataSize, uint8_t _addressSize) :
345 %(base_class)s(machInst, "%(mnemonic)s", instMnem,
346 isMicro, isDelayed, isFirst, isLast,
347 _scale, _index, _base,
348 _disp, _segment, _data,
349 _dataSize, _addressSize, %(op_class)s)
350 {
351 buildMe();
352 }
353}};
354
355let {{
356 class LdStOp(X86Microop):
357 def __init__(self, data, segment, addr, disp, dataSize, addressSize):
358 self.data = data
359 [self.scale, self.index, self.base] = addr
360 self.disp = disp
361 self.segment = segment
362 self.dataSize = dataSize
363 self.addressSize = addressSize
364
365 def getAllocator(self, *microFlags):
366 allocator = '''new %(class_name)s(machInst, macrocodeBlock
367 %(flags)s, %(scale)s, %(index)s, %(base)s,
368 %(disp)s, %(segment)s, %(data)s,
369 %(dataSize)s, %(addressSize)s)''' % {
370 "class_name" : self.className,
371 "flags" : self.microFlagsText(microFlags),
372 "scale" : self.scale, "index" : self.index,
373 "base" : self.base,
374 "disp" : self.disp,
375 "segment" : self.segment, "data" : self.data,
376 "dataSize" : self.dataSize, "addressSize" : self.addressSize}
377 return allocator
378}};
379
380let {{
381
382 # Make these empty strings so that concatenating onto
383 # them will always work.
384 header_output = ""
385 decoder_output = ""
386 exec_output = ""
387
388 calculateEA = "EA = SegBase + scale * Index + Base + disp;"
389
390 def defineMicroLoadOp(mnemonic, code, mem_flags=0):
391 global header_output
392 global decoder_output
393 global exec_output
394 global microopClasses
395 Name = mnemonic
396 name = mnemonic.lower()
397
398 # Build up the all register version of this micro op
399 iop = InstObjParams(name, Name, 'X86ISA::LdStOp',
400 {"code": code,
401 "ea_code": calculateEA,
402 "mem_flags": mem_flags})
403 header_output += MicroLdStOpDeclare.subst(iop)
404 decoder_output += MicroLdStOpConstructor.subst(iop)
405 exec_output += MicroLoadExecute.subst(iop)
406 exec_output += MicroLoadInitiateAcc.subst(iop)
407 exec_output += MicroLoadCompleteAcc.subst(iop)
408
409 class LoadOp(LdStOp):
410 def __init__(self, data, segment, addr, disp = 0,
411 dataSize="env.dataSize", addressSize="env.addressSize"):
412 super(LoadOp, self).__init__(data, segment,
413 addr, disp, dataSize, addressSize)
414 self.className = Name
415 self.mnemonic = name
416
417 microopClasses[name] = LoadOp
418
419 defineMicroLoadOp('Ld', 'Data = merge(Data, Mem, dataSize);')
420 defineMicroLoadOp('Ldst', 'Data = merge(Data, Mem, dataSize);', 'StoreCheck')
421 defineMicroLoadOp('Ldfp', 'FpData.uqw = Mem;')
422
423 def defineMicroStoreOp(mnemonic, code, \
424 postCode="", completeCode="", mem_flags=0):
425 global header_output
426 global decoder_output
427 global exec_output
428 global microopClasses
429 Name = mnemonic
430 name = mnemonic.lower()
431
432 # Build up the all register version of this micro op
433 iop = InstObjParams(name, Name, 'X86ISA::LdStOp',
434 {"code": code,
435 "post_code": postCode,
436 "complete_code": completeCode,
437 "ea_code": calculateEA,
438 "mem_flags": mem_flags})
439 header_output += MicroLdStOpDeclare.subst(iop)
440 decoder_output += MicroLdStOpConstructor.subst(iop)
441 exec_output += MicroStoreExecute.subst(iop)
442 exec_output += MicroStoreInitiateAcc.subst(iop)
443 exec_output += MicroStoreCompleteAcc.subst(iop)
444
445 class StoreOp(LdStOp):
446 def __init__(self, data, segment, addr, disp = 0,
447 dataSize="env.dataSize", addressSize="env.addressSize"):
448 super(StoreOp, self).__init__(data, segment,
449 addr, disp, dataSize, addressSize)
450 self.className = Name
451 self.mnemonic = name
452
453 microopClasses[name] = StoreOp
454
455 defineMicroStoreOp('St', 'Mem = Data;')
456 defineMicroStoreOp('Stfp', 'Mem = FpData.uqw;')
457 defineMicroStoreOp('Stupd', 'Mem = Data;',
458 'Base = merge(Base, EA - SegBase, addressSize);',
459 'Base = merge(Base, pkt->req->getVaddr() - SegBase, addressSize);');
460 defineMicroStoreOp('Cda', 'Mem = 0;', mem_flags="Request::NO_ACCESS")
461
462 iop = InstObjParams("lea", "Lea", 'X86ISA::LdStOp',
463 {"code": "Data = merge(Data, EA, dataSize);",
464 "ea_code": calculateEA,
465 "mem_flags": 0})
466 header_output += MicroLeaDeclare.subst(iop)
467 decoder_output += MicroLdStOpConstructor.subst(iop)
468 exec_output += MicroLeaExecute.subst(iop)
469
470 class LeaOp(LdStOp):
471 def __init__(self, data, segment, addr, disp = 0,
472 dataSize="env.dataSize", addressSize="env.addressSize"):
473 super(LeaOp, self).__init__(data, segment,
474 addr, disp, dataSize, addressSize)
475 self.className = "Lea"
476 self.mnemonic = "lea"
477
478 microopClasses["lea"] = LeaOp
479
480
481 iop = InstObjParams("tia", "Tia", 'X86ISA::LdStOp',
482 {"code": "xc->demapPage(EA, 0);",
483 "ea_code": calculateEA,
484 "mem_flags": 0})
485 header_output += MicroLeaDeclare.subst(iop)
486 decoder_output += MicroLdStOpConstructor.subst(iop)
487 exec_output += MicroLeaExecute.subst(iop)
488
489 class TiaOp(LdStOp):
490 def __init__(self, segment, addr, disp = 0,
491 dataSize="env.dataSize", addressSize="env.addressSize"):
492 super(TiaOp, self).__init__("NUM_INTREGS", segment,
493 addr, disp, dataSize, addressSize)
494 self.className = "Tia"
495 self.mnemonic = "tia"
496
497 microopClasses["tia"] = TiaOp
498
499 class CdaOp(LdStOp):
500 def __init__(self, segment, addr, disp = 0,
501 dataSize="env.dataSize", addressSize="env.addressSize"):
502 super(CdaOp, self).__init__("NUM_INTREGS", segment,
503 addr, disp, dataSize, addressSize)
504 self.className = "Cda"
505 self.mnemonic = "cda"
506
507 microopClasses["cda"] = CdaOp
508}};
509