1// Copyright (c) 2007-2008 The Hewlett-Packard Development Company
2// Copyright (c) 2015 Advanced Micro Devices, Inc.
3// All rights reserved.
4//
5// The license below extends only to copyright in the software and shall
6// not be construed as granting a license to any other intellectual
7// property including but not limited to intellectual property relating
8// to a hardware implementation of the functionality of the software

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310 {
311 %(constructor)s;
312 }
313}};
314
315let {{
316 class LdStOp(X86Microop):
317 def __init__(self, data, segment, addr, disp,
318 dataSize, addressSize, baseFlags, atCPL0, prefetch, nonSpec):
319 self.data = data
320 [self.scale, self.index, self.base] = addr
321 self.disp = disp
322 self.segment = segment
323 self.dataSize = dataSize
324 self.addressSize = addressSize
325 self.memFlags = baseFlags
326 if atCPL0:
327 self.memFlags += " | (CPL0FlagBit << FlagShift)"
328 self.instFlags = ""
329 if prefetch:
330 self.memFlags += " | Request::PREFETCH"
331 self.instFlags += " | (1ULL << StaticInst::IsDataPrefetch)"
332 if nonSpec:
333 self.instFlags += " | (1ULL << StaticInst::IsNonSpeculative)"
334 self.memFlags += " | (machInst.legacy.addr ? " + \
335 "(AddrSizeFlagBit << FlagShift) : 0)"
336
337 def getAllocator(self, microFlags):
338 allocator = '''new %(class_name)s(machInst, macrocodeBlock,
339 %(flags)s, %(scale)s, %(index)s, %(base)s,
340 %(disp)s, %(segment)s, %(data)s,
341 %(dataSize)s, %(addressSize)s, %(memFlags)s)''' % {
342 "class_name" : self.className,
343 "flags" : self.microFlagsText(microFlags) + self.instFlags,
344 "scale" : self.scale, "index" : self.index,
345 "base" : self.base,
346 "disp" : self.disp,
347 "segment" : self.segment, "data" : self.data,
348 "dataSize" : self.dataSize, "addressSize" : self.addressSize,
349 "memFlags" : self.memFlags}
350 return allocator
351
352 class BigLdStOp(X86Microop):
353 def __init__(self, data, segment, addr, disp,
354 dataSize, addressSize, baseFlags, atCPL0, prefetch, nonSpec):
355 self.data = data
356 [self.scale, self.index, self.base] = addr
357 self.disp = disp
358 self.segment = segment
359 self.dataSize = dataSize
360 self.addressSize = addressSize
361 self.memFlags = baseFlags
362 if atCPL0:
363 self.memFlags += " | (CPL0FlagBit << FlagShift)"
364 self.instFlags = ""
365 if prefetch:
366 self.memFlags += " | Request::PREFETCH"
367 self.instFlags += " | (1ULL << StaticInst::IsDataPrefetch)"
368 if nonSpec:
369 self.instFlags += " | (1ULL << StaticInst::IsNonSpeculative)"
370 self.memFlags += " | (machInst.legacy.addr ? " + \
371 "(AddrSizeFlagBit << FlagShift) : 0)"
372
373 def getAllocator(self, microFlags):
374 allocString = '''
375 (%(dataSize)s >= 4) ?
376 (StaticInstPtr)(new %(class_name)sBig(machInst,
377 macrocodeBlock, %(flags)s, %(scale)s, %(index)s,
378 %(base)s, %(disp)s, %(segment)s, %(data)s,
379 %(dataSize)s, %(addressSize)s, %(memFlags)s)) :

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390 "disp" : self.disp,
391 "segment" : self.segment, "data" : self.data,
392 "dataSize" : self.dataSize, "addressSize" : self.addressSize,
393 "memFlags" : self.memFlags}
394 return allocator
395
396 class LdStSplitOp(LdStOp):
397 def __init__(self, data, segment, addr, disp,
398 dataSize, addressSize, baseFlags, atCPL0, prefetch, nonSpec):
399 super(LdStSplitOp, self).__init__(0, segment, addr, disp,
400 dataSize, addressSize, baseFlags, atCPL0, prefetch, nonSpec)
401 (self.dataLow, self.dataHi) = data
402
403 def getAllocator(self, microFlags):
404 allocString = '''(StaticInstPtr)(new %(class_name)s(machInst,
405 macrocodeBlock, %(flags)s, %(scale)s, %(index)s,
406 %(base)s, %(disp)s, %(segment)s,
407 %(dataLow)s, %(dataHi)s,
408 %(dataSize)s, %(addressSize)s, %(memFlags)s))

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430 exec_output = ""
431
432 segmentEAExpr = \
433 'bits(scale * Index + Base + disp, addressSize * 8 - 1, 0);'
434
435 calculateEA = 'EA = SegBase + ' + segmentEAExpr
436
437 def defineMicroLoadOp(mnemonic, code, bigCode='',
438 mem_flags="0", big=True, nonSpec=False):
439 global header_output
440 global decoder_output
441 global exec_output
442 global microopClasses
443 Name = mnemonic
444 name = mnemonic.lower()
445
446 # Build up the all register version of this micro op

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455 "memDataSize": "dataSize" })]
456 for iop in iops:
457 header_output += MicroLdStOpDeclare.subst(iop)
458 decoder_output += MicroLdStOpConstructor.subst(iop)
459 exec_output += MicroLoadExecute.subst(iop)
460 exec_output += MicroLoadInitiateAcc.subst(iop)
461 exec_output += MicroLoadCompleteAcc.subst(iop)
462
463 base = LdStOp
464 if big:
465 base = BigLdStOp
466 class LoadOp(base):
467 def __init__(self, data, segment, addr, disp = 0,
468 dataSize="env.dataSize",
469 addressSize="env.addressSize",
470 atCPL0=False, prefetch=False, nonSpec=nonSpec):
471 super(LoadOp, self).__init__(data, segment, addr,
472 disp, dataSize, addressSize, mem_flags,
473 atCPL0, prefetch, nonSpec)
474 self.className = Name
475 self.mnemonic = name
476
477 microopClasses[name] = LoadOp
478
479 defineMicroLoadOp('Ld', 'Data = merge(Data, Mem, dataSize);',
480 'Data = Mem & mask(dataSize * 8);')
481 defineMicroLoadOp('Ldst', 'Data = merge(Data, Mem, dataSize);',
482 'Data = Mem & mask(dataSize * 8);',
483 '(StoreCheck << FlagShift)')
484 defineMicroLoadOp('Ldstl', 'Data = merge(Data, Mem, dataSize);',
485 'Data = Mem & mask(dataSize * 8);',
486 '(StoreCheck << FlagShift) | Request::LOCKED_RMW',
487 nonSpec=True)
488

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539 exec_output += MicroLoadExecute.subst(iop)
540 exec_output += MicroLoadInitiateAcc.subst(iop)
541 exec_output += MicroLoadCompleteAcc.subst(iop)
542
543 class LoadOp(LdStSplitOp):
544 def __init__(self, data, segment, addr, disp = 0,
545 dataSize="env.dataSize",
546 addressSize="env.addressSize",
547 atCPL0=False, prefetch=False, nonSpec=nonSpec):
548 super(LoadOp, self).__init__(data, segment, addr,
549 disp, dataSize, addressSize, mem_flags,
550 atCPL0, prefetch, nonSpec)
551 self.className = Name
552 self.mnemonic = name
553
554 microopClasses[name] = LoadOp
555
556 code = '''
557 switch (dataSize) {
558 case 4:

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569
570 defineMicroLoadSplitOp('LdSplit', code,
571 '(StoreCheck << FlagShift)')
572
573 defineMicroLoadSplitOp('LdSplitl', code,
574 '(StoreCheck << FlagShift) | Request::LOCKED_RMW',
575 nonSpec=True)
576
577 def defineMicroStoreOp(mnemonic, code, completeCode="", mem_flags="0"):
578 global header_output
579 global decoder_output
580 global exec_output
581 global microopClasses
582 Name = mnemonic
583 name = mnemonic.lower()
584
585 # Build up the all register version of this micro op
586 iop = InstObjParams(name, Name, 'X86ISA::LdStOp',
587 { "code": code,
588 "complete_code": completeCode,
589 "ea_code": calculateEA,
590 "memDataSize": "dataSize" })
591 header_output += MicroLdStOpDeclare.subst(iop)
592 decoder_output += MicroLdStOpConstructor.subst(iop)
593 exec_output += MicroStoreExecute.subst(iop)
594 exec_output += MicroStoreInitiateAcc.subst(iop)
595 exec_output += MicroStoreCompleteAcc.subst(iop)
596
597 class StoreOp(LdStOp):
598 def __init__(self, data, segment, addr, disp = 0,
599 dataSize="env.dataSize",
600 addressSize="env.addressSize",
601 atCPL0=False, nonSpec=False):
602 super(StoreOp, self).__init__(data, segment, addr, disp,
603 dataSize, addressSize, mem_flags, atCPL0, False,
604 nonSpec)
605 self.className = Name
606 self.mnemonic = name
607
608 microopClasses[name] = StoreOp
609
610 defineMicroStoreOp('St', 'Mem = pick(Data, 2, dataSize);')
611 defineMicroStoreOp('Stul', 'Mem = pick(Data, 2, dataSize);',
612 mem_flags="Request::LOCKED_RMW")
613
614 defineMicroStoreOp('Stfp', code='Mem = FpData_uqw;')
615
616 defineMicroStoreOp('Stfp87', code='''
617 switch (dataSize)
618 {

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650 exec_output += MicroStoreExecute.subst(iop)
651 exec_output += MicroStoreInitiateAcc.subst(iop)
652 exec_output += MicroStoreCompleteAcc.subst(iop)
653
654 class StoreOp(LdStSplitOp):
655 def __init__(self, data, segment, addr, disp = 0,
656 dataSize="env.dataSize",
657 addressSize="env.addressSize",
658 atCPL0=False, nonSpec=False):
659 super(StoreOp, self).__init__(data, segment, addr, disp,
660 dataSize, addressSize, mem_flags, atCPL0, False,
661 nonSpec)
662 self.className = Name
663 self.mnemonic = name
664
665 microopClasses[name] = StoreOp
666
667 code = '''
668 switch (dataSize) {
669 case 4:

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689 header_output += MicroLeaDeclare.subst(iop)
690 decoder_output += MicroLdStOpConstructor.subst(iop)
691 exec_output += MicroLeaExecute.subst(iop)
692
693 class LeaOp(LdStOp):
694 def __init__(self, data, segment, addr, disp = 0,
695 dataSize="env.dataSize", addressSize="env.addressSize"):
696 super(LeaOp, self).__init__(data, segment, addr, disp,
697 dataSize, addressSize, "0", False, False, False)
698 self.className = "Lea"
699 self.mnemonic = "lea"
700
701 microopClasses["lea"] = LeaOp
702
703
704 iop = InstObjParams("tia", "Tia", 'X86ISA::LdStOp',
705 { "code": "xc->demapPage(EA, 0);",

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710 exec_output += MicroLeaExecute.subst(iop)
711
712 class TiaOp(LdStOp):
713 def __init__(self, segment, addr, disp = 0,
714 dataSize="env.dataSize",
715 addressSize="env.addressSize"):
716 super(TiaOp, self).__init__("InstRegIndex(NUM_INTREGS)", segment,
717 addr, disp, dataSize, addressSize, "0", False, False,
718 False)
719 self.className = "Tia"
720 self.mnemonic = "tia"
721
722 microopClasses["tia"] = TiaOp
723
724 class CdaOp(LdStOp):
725 def __init__(self, segment, addr, disp = 0,
726 dataSize="env.dataSize",
727 addressSize="env.addressSize", atCPL0=False):
728 super(CdaOp, self).__init__("InstRegIndex(NUM_INTREGS)", segment,
729 addr, disp, dataSize, addressSize, "Request::NO_ACCESS",
730 atCPL0, False, False)
731 self.className = "Cda"
732 self.mnemonic = "cda"
733
734 microopClasses["cda"] = CdaOp
735}};
736