1// Copyright (c) 2007-2008 The Hewlett-Packard Development Company
2// All rights reserved.
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license
9// terms below provided that you ensure that this notice is replicated
--- 83 unchanged lines hidden (view full) ---
93 Fault fault = NoFault;
94 Addr EA;
95
96 %(op_decl)s;
97 %(op_rd)s;
98 %(ea_code)s;
99 DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
100
101 fault = readMemAtomic(xc, traceData, EA, Mem, dataSize, memFlags);
102
103 if (fault == NoFault) {
104 %(code)s;
105 } else if (memFlags & Request::PREFETCH) {
106 // For prefetches, ignore any faults/exceptions.
107 return NoFault;
108 }
109 if(fault == NoFault)
--- 12 unchanged lines hidden (view full) ---
122 Fault fault = NoFault;
123 Addr EA;
124
125 %(op_decl)s;
126 %(op_rd)s;
127 %(ea_code)s;
128 DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
129
130 fault = initiateMemRead(xc, traceData, EA, dataSize, memFlags);
131
132 return fault;
133 }
134}};
135
136def template MicroLoadCompleteAcc {{
137 Fault %(class_name)s::completeAcc(PacketPtr pkt,
138 CPU_EXEC_CONTEXT * xc,
139 Trace::InstRecord * traceData) const
140 {
141 Fault fault = NoFault;
142
143 %(op_decl)s;
144 %(op_rd)s;
145
146 getMem(pkt, Mem, dataSize, traceData);
147
148 %(code)s;
149
150 if(fault == NoFault)
151 {
152 %(op_wb)s;
153 }
154
--- 14 unchanged lines hidden (view full) ---
169 %(op_rd)s;
170 %(ea_code)s;
171 DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
172
173 %(code)s;
174
175 if(fault == NoFault)
176 {
177 fault = writeMemAtomic(xc, traceData, Mem, dataSize, EA,
178 memFlags, NULL);
179 if(fault == NoFault)
180 {
181 %(op_wb)s;
182 }
183 }
184
185 return fault;
--- 11 unchanged lines hidden (view full) ---
197 %(op_rd)s;
198 %(ea_code)s;
199 DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
200
201 %(code)s;
202
203 if(fault == NoFault)
204 {
205 fault = writeMemTiming(xc, traceData, Mem, dataSize, EA,
206 memFlags, NULL);
207 }
208 return fault;
209 }
210}};
211
212def template MicroStoreCompleteAcc {{
213 Fault %(class_name)s::completeAcc(PacketPtr pkt,
--- 34 unchanged lines hidden (view full) ---
248 %(BasicExecDeclare)s
249
250 %(InitiateAccDeclare)s
251
252 %(CompleteAccDeclare)s
253 };
254}};
255
256def template MicroLdStOpConstructor {{
257 %(class_name)s::%(class_name)s(
258 ExtMachInst machInst, const char * instMnem, uint64_t setFlags,
259 uint8_t _scale, InstRegIndex _index, InstRegIndex _base,
260 uint64_t _disp, InstRegIndex _segment,
261 InstRegIndex _data,
262 uint8_t _dataSize, uint8_t _addressSize,
263 Request::FlagsType _memFlags) :
264 %(base_class)s(machInst, "%(mnemonic)s", instMnem, setFlags,
265 _scale, _index, _base,
266 _disp, _segment, _data,
267 _dataSize, _addressSize, _memFlags, %(op_class)s)
268 {
269 %(constructor)s;
270 }
271}};
272
273let {{
274 class LdStOp(X86Microop):
275 def __init__(self, data, segment, addr, disp,
276 dataSize, addressSize, baseFlags, atCPL0, prefetch, nonSpec):
277 self.data = data
278 [self.scale, self.index, self.base] = addr
279 self.disp = disp
280 self.segment = segment
--- 64 unchanged lines hidden (view full) ---
345 "flags" : self.microFlagsText(microFlags) + self.instFlags,
346 "scale" : self.scale, "index" : self.index,
347 "base" : self.base,
348 "disp" : self.disp,
349 "segment" : self.segment, "data" : self.data,
350 "dataSize" : self.dataSize, "addressSize" : self.addressSize,
351 "memFlags" : self.memFlags}
352 return allocator
353}};
354
355let {{
356
357 # Make these empty strings so that concatenating onto
358 # them will always work.
359 header_output = ""
360 decoder_output = ""
361 exec_output = ""
362
363 calculateEA = '''
364 EA = SegBase + bits(scale * Index + Base + disp, addressSize * 8 - 1, 0);
365 '''
366
367 def defineMicroLoadOp(mnemonic, code, bigCode='',
368 mem_flags="0", big=True):
369 global header_output
370 global decoder_output
371 global exec_output
372 global microopClasses
373 Name = mnemonic
374 name = mnemonic.lower()
375
376 # Build up the all register version of this micro op
377 iops = [InstObjParams(name, Name, 'X86ISA::LdStOp',
378 {"code": code, "ea_code": calculateEA})]
379 if big:
380 iops += [InstObjParams(name, Name + "Big", 'X86ISA::LdStOp',
381 {"code": bigCode, "ea_code": calculateEA})]
382 for iop in iops:
383 header_output += MicroLdStOpDeclare.subst(iop)
384 decoder_output += MicroLdStOpConstructor.subst(iop)
385 exec_output += MicroLoadExecute.subst(iop)
386 exec_output += MicroLoadInitiateAcc.subst(iop)
387 exec_output += MicroLoadCompleteAcc.subst(iop)
388
389 base = LdStOp
390 if big:
391 base = BigLdStOp
392 class LoadOp(base):
393 def __init__(self, data, segment, addr, disp = 0,
394 dataSize="env.dataSize",
395 addressSize="env.addressSize",
396 atCPL0=False, prefetch=False, nonSpec=False):
397 super(LoadOp, self).__init__(data, segment, addr,
398 disp, dataSize, addressSize, mem_flags,
399 atCPL0, prefetch, nonSpec)
400 self.className = Name
401 self.mnemonic = name
402
403 microopClasses[name] = LoadOp
404
405 defineMicroLoadOp('Ld', 'Data = merge(Data, Mem, dataSize);',
406 'Data = Mem & mask(dataSize * 8);')
407 defineMicroLoadOp('Ldst', 'Data = merge(Data, Mem, dataSize);',
408 'Data = Mem & mask(dataSize * 8);',
409 '(StoreCheck << FlagShift)')
410 defineMicroLoadOp('Ldstl', 'Data = merge(Data, Mem, dataSize);',
411 'Data = Mem & mask(dataSize * 8);',
412 '(StoreCheck << FlagShift) | Request::LOCKED_RMW')
413
414 defineMicroLoadOp('Ldfp', code='FpData_uqw = Mem', big = False)
415
416 defineMicroLoadOp('Ldfp87', code='''
417 switch (dataSize)
418 {
419 case 4:
420 FpData_df = *(float *)&Mem;
--- 20 unchanged lines hidden (view full) ---
441 case 8:
442 FpData_df = (int64_t)Mem;
443 break;
444 default:
445 panic("Unhandled data size in LdIFp87.\\n");
446 }
447 ''', big = False)
448
449 def defineMicroStoreOp(mnemonic, code, completeCode="", mem_flags="0"):
450 global header_output
451 global decoder_output
452 global exec_output
453 global microopClasses
454 Name = mnemonic
455 name = mnemonic.lower()
456
457 # Build up the all register version of this micro op
458 iop = InstObjParams(name, Name, 'X86ISA::LdStOp',
459 {"code": code,
460 "complete_code": completeCode,
461 "ea_code": calculateEA})
462 header_output += MicroLdStOpDeclare.subst(iop)
463 decoder_output += MicroLdStOpConstructor.subst(iop)
464 exec_output += MicroStoreExecute.subst(iop)
465 exec_output += MicroStoreInitiateAcc.subst(iop)
466 exec_output += MicroStoreCompleteAcc.subst(iop)
467
468 class StoreOp(LdStOp):
469 def __init__(self, data, segment, addr, disp = 0,
--- 26 unchanged lines hidden (view full) ---
496 break;
497 default:
498 panic("Unhandled data size in StFp87.\\n");
499 }
500 ''')
501
502 defineMicroStoreOp('Cda', 'Mem = 0;', mem_flags="Request::NO_ACCESS")
503
504 iop = InstObjParams("lea", "Lea", 'X86ISA::LdStOp',
505 {"code": "Data = merge(Data, EA, dataSize);",
506 "ea_code": '''
507 EA = bits(scale * Index + Base + disp, addressSize * 8 - 1, 0);
508 '''})
509 header_output += MicroLeaDeclare.subst(iop)
510 decoder_output += MicroLdStOpConstructor.subst(iop)
511 exec_output += MicroLeaExecute.subst(iop)
512
513 class LeaOp(LdStOp):
514 def __init__(self, data, segment, addr, disp = 0,
515 dataSize="env.dataSize", addressSize="env.addressSize"):
516 super(LeaOp, self).__init__(data, segment, addr, disp,
517 dataSize, addressSize, "0", False, False, False)
518 self.className = "Lea"
519 self.mnemonic = "lea"
520
521 microopClasses["lea"] = LeaOp
522
523
524 iop = InstObjParams("tia", "Tia", 'X86ISA::LdStOp',
525 {"code": "xc->demapPage(EA, 0);",
526 "ea_code": calculateEA})
527 header_output += MicroLeaDeclare.subst(iop)
528 decoder_output += MicroLdStOpConstructor.subst(iop)
529 exec_output += MicroLeaExecute.subst(iop)
530
531 class TiaOp(LdStOp):
532 def __init__(self, segment, addr, disp = 0,
533 dataSize="env.dataSize",
534 addressSize="env.addressSize"):
--- 21 unchanged lines hidden ---
2// All rights reserved.
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license
9// terms below provided that you ensure that this notice is replicated
--- 83 unchanged lines hidden (view full) ---
93 Fault fault = NoFault;
94 Addr EA;
95
96 %(op_decl)s;
97 %(op_rd)s;
98 %(ea_code)s;
99 DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
100
101 fault = readMemAtomic(xc, traceData, EA, Mem, dataSize, memFlags);
102
103 if (fault == NoFault) {
104 %(code)s;
105 } else if (memFlags & Request::PREFETCH) {
106 // For prefetches, ignore any faults/exceptions.
107 return NoFault;
108 }
109 if(fault == NoFault)
--- 12 unchanged lines hidden (view full) ---
122 Fault fault = NoFault;
123 Addr EA;
124
125 %(op_decl)s;
126 %(op_rd)s;
127 %(ea_code)s;
128 DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
129
130 fault = initiateMemRead(xc, traceData, EA, dataSize, memFlags);
131
132 return fault;
133 }
134}};
135
136def template MicroLoadCompleteAcc {{
137 Fault %(class_name)s::completeAcc(PacketPtr pkt,
138 CPU_EXEC_CONTEXT * xc,
139 Trace::InstRecord * traceData) const
140 {
141 Fault fault = NoFault;
142
143 %(op_decl)s;
144 %(op_rd)s;
145
146 getMem(pkt, Mem, dataSize, traceData);
147
148 %(code)s;
149
150 if(fault == NoFault)
151 {
152 %(op_wb)s;
153 }
154
--- 14 unchanged lines hidden (view full) ---
169 %(op_rd)s;
170 %(ea_code)s;
171 DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
172
173 %(code)s;
174
175 if(fault == NoFault)
176 {
177 fault = writeMemAtomic(xc, traceData, Mem, dataSize, EA,
178 memFlags, NULL);
179 if(fault == NoFault)
180 {
181 %(op_wb)s;
182 }
183 }
184
185 return fault;
--- 11 unchanged lines hidden (view full) ---
197 %(op_rd)s;
198 %(ea_code)s;
199 DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
200
201 %(code)s;
202
203 if(fault == NoFault)
204 {
205 fault = writeMemTiming(xc, traceData, Mem, dataSize, EA,
206 memFlags, NULL);
207 }
208 return fault;
209 }
210}};
211
212def template MicroStoreCompleteAcc {{
213 Fault %(class_name)s::completeAcc(PacketPtr pkt,
--- 34 unchanged lines hidden (view full) ---
248 %(BasicExecDeclare)s
249
250 %(InitiateAccDeclare)s
251
252 %(CompleteAccDeclare)s
253 };
254}};
255
256def template MicroLdStOpConstructor {{
257 %(class_name)s::%(class_name)s(
258 ExtMachInst machInst, const char * instMnem, uint64_t setFlags,
259 uint8_t _scale, InstRegIndex _index, InstRegIndex _base,
260 uint64_t _disp, InstRegIndex _segment,
261 InstRegIndex _data,
262 uint8_t _dataSize, uint8_t _addressSize,
263 Request::FlagsType _memFlags) :
264 %(base_class)s(machInst, "%(mnemonic)s", instMnem, setFlags,
265 _scale, _index, _base,
266 _disp, _segment, _data,
267 _dataSize, _addressSize, _memFlags, %(op_class)s)
268 {
269 %(constructor)s;
270 }
271}};
272
273let {{
274 class LdStOp(X86Microop):
275 def __init__(self, data, segment, addr, disp,
276 dataSize, addressSize, baseFlags, atCPL0, prefetch, nonSpec):
277 self.data = data
278 [self.scale, self.index, self.base] = addr
279 self.disp = disp
280 self.segment = segment
--- 64 unchanged lines hidden (view full) ---
345 "flags" : self.microFlagsText(microFlags) + self.instFlags,
346 "scale" : self.scale, "index" : self.index,
347 "base" : self.base,
348 "disp" : self.disp,
349 "segment" : self.segment, "data" : self.data,
350 "dataSize" : self.dataSize, "addressSize" : self.addressSize,
351 "memFlags" : self.memFlags}
352 return allocator
353}};
354
355let {{
356
357 # Make these empty strings so that concatenating onto
358 # them will always work.
359 header_output = ""
360 decoder_output = ""
361 exec_output = ""
362
363 calculateEA = '''
364 EA = SegBase + bits(scale * Index + Base + disp, addressSize * 8 - 1, 0);
365 '''
366
367 def defineMicroLoadOp(mnemonic, code, bigCode='',
368 mem_flags="0", big=True):
369 global header_output
370 global decoder_output
371 global exec_output
372 global microopClasses
373 Name = mnemonic
374 name = mnemonic.lower()
375
376 # Build up the all register version of this micro op
377 iops = [InstObjParams(name, Name, 'X86ISA::LdStOp',
378 {"code": code, "ea_code": calculateEA})]
379 if big:
380 iops += [InstObjParams(name, Name + "Big", 'X86ISA::LdStOp',
381 {"code": bigCode, "ea_code": calculateEA})]
382 for iop in iops:
383 header_output += MicroLdStOpDeclare.subst(iop)
384 decoder_output += MicroLdStOpConstructor.subst(iop)
385 exec_output += MicroLoadExecute.subst(iop)
386 exec_output += MicroLoadInitiateAcc.subst(iop)
387 exec_output += MicroLoadCompleteAcc.subst(iop)
388
389 base = LdStOp
390 if big:
391 base = BigLdStOp
392 class LoadOp(base):
393 def __init__(self, data, segment, addr, disp = 0,
394 dataSize="env.dataSize",
395 addressSize="env.addressSize",
396 atCPL0=False, prefetch=False, nonSpec=False):
397 super(LoadOp, self).__init__(data, segment, addr,
398 disp, dataSize, addressSize, mem_flags,
399 atCPL0, prefetch, nonSpec)
400 self.className = Name
401 self.mnemonic = name
402
403 microopClasses[name] = LoadOp
404
405 defineMicroLoadOp('Ld', 'Data = merge(Data, Mem, dataSize);',
406 'Data = Mem & mask(dataSize * 8);')
407 defineMicroLoadOp('Ldst', 'Data = merge(Data, Mem, dataSize);',
408 'Data = Mem & mask(dataSize * 8);',
409 '(StoreCheck << FlagShift)')
410 defineMicroLoadOp('Ldstl', 'Data = merge(Data, Mem, dataSize);',
411 'Data = Mem & mask(dataSize * 8);',
412 '(StoreCheck << FlagShift) | Request::LOCKED_RMW')
413
414 defineMicroLoadOp('Ldfp', code='FpData_uqw = Mem', big = False)
415
416 defineMicroLoadOp('Ldfp87', code='''
417 switch (dataSize)
418 {
419 case 4:
420 FpData_df = *(float *)&Mem;
--- 20 unchanged lines hidden (view full) ---
441 case 8:
442 FpData_df = (int64_t)Mem;
443 break;
444 default:
445 panic("Unhandled data size in LdIFp87.\\n");
446 }
447 ''', big = False)
448
449 def defineMicroStoreOp(mnemonic, code, completeCode="", mem_flags="0"):
450 global header_output
451 global decoder_output
452 global exec_output
453 global microopClasses
454 Name = mnemonic
455 name = mnemonic.lower()
456
457 # Build up the all register version of this micro op
458 iop = InstObjParams(name, Name, 'X86ISA::LdStOp',
459 {"code": code,
460 "complete_code": completeCode,
461 "ea_code": calculateEA})
462 header_output += MicroLdStOpDeclare.subst(iop)
463 decoder_output += MicroLdStOpConstructor.subst(iop)
464 exec_output += MicroStoreExecute.subst(iop)
465 exec_output += MicroStoreInitiateAcc.subst(iop)
466 exec_output += MicroStoreCompleteAcc.subst(iop)
467
468 class StoreOp(LdStOp):
469 def __init__(self, data, segment, addr, disp = 0,
--- 26 unchanged lines hidden (view full) ---
496 break;
497 default:
498 panic("Unhandled data size in StFp87.\\n");
499 }
500 ''')
501
502 defineMicroStoreOp('Cda', 'Mem = 0;', mem_flags="Request::NO_ACCESS")
503
504 iop = InstObjParams("lea", "Lea", 'X86ISA::LdStOp',
505 {"code": "Data = merge(Data, EA, dataSize);",
506 "ea_code": '''
507 EA = bits(scale * Index + Base + disp, addressSize * 8 - 1, 0);
508 '''})
509 header_output += MicroLeaDeclare.subst(iop)
510 decoder_output += MicroLdStOpConstructor.subst(iop)
511 exec_output += MicroLeaExecute.subst(iop)
512
513 class LeaOp(LdStOp):
514 def __init__(self, data, segment, addr, disp = 0,
515 dataSize="env.dataSize", addressSize="env.addressSize"):
516 super(LeaOp, self).__init__(data, segment, addr, disp,
517 dataSize, addressSize, "0", False, False, False)
518 self.className = "Lea"
519 self.mnemonic = "lea"
520
521 microopClasses["lea"] = LeaOp
522
523
524 iop = InstObjParams("tia", "Tia", 'X86ISA::LdStOp',
525 {"code": "xc->demapPage(EA, 0);",
526 "ea_code": calculateEA})
527 header_output += MicroLeaDeclare.subst(iop)
528 decoder_output += MicroLdStOpConstructor.subst(iop)
529 exec_output += MicroLeaExecute.subst(iop)
530
531 class TiaOp(LdStOp):
532 def __init__(self, segment, addr, disp = 0,
533 dataSize="env.dataSize",
534 addressSize="env.addressSize"):
--- 21 unchanged lines hidden ---