1// Copyright (c) 2007 The Hewlett-Packard Development Company
2// Copyright (c) 2012-2013 Mark D. Hill and David A. Wood
3// All rights reserved.
4//
5// The license below extends only to copyright in the software and shall
6// not be construed as granting a license to any other intellectual
7// property including but not limited to intellectual property relating
8// to a hardware implementation of the functionality of the software
9// licensed hereunder. You may use the software subject to the license
10// terms below provided that you ensure that this notice is replicated
11// unmodified and in its entirety in all distributions of the software,
12// modified or unmodified, in source code or in binary form.
13//
14// Redistribution and use in source and binary forms, with or without
15// modification, are permitted provided that the following conditions are
16// met: redistributions of source code must retain the above copyright
17// notice, this list of conditions and the following disclaimer;
18// redistributions in binary form must reproduce the above copyright
19// notice, this list of conditions and the following disclaimer in the
20// documentation and/or other materials provided with the distribution;
21// neither the name of the copyright holders nor the names of its
22// contributors may be used to endorse or promote products derived from
23// this software without specific prior written permission.
24//
25// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36//
37// Authors: Gabe Black
38// Nilay Vaish
39
40//////////////////////////////////////////////////////////////////////////
41//
42// FpOp Microop templates
43//
44//////////////////////////////////////////////////////////////////////////
45
46def template MicroFpOpExecute {{
47 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
48 Trace::InstRecord *traceData) const
49 {
50 Fault fault = NoFault;
51
52 DPRINTF(X86, "The data size is %d\n", dataSize);
53 %(op_decl)s;
54 %(op_rd)s;
55
56 if(%(cond_check)s)
57 {
58 %(code)s;
59 %(flag_code)s;
60 %(tag_code)s;
61 %(top_code)s;
62 }
63 else
64 {
65 %(else_code)s;
66 }
67
68 //Write the resulting state to the execution context
69 if(fault == NoFault)
70 {
71 %(op_wb)s;
72 }
73 return fault;
74 }
75}};
76
77def template MicroFpOpDeclare {{
78 class %(class_name)s : public %(base_class)s
79 {
80 public:
81 %(class_name)s(ExtMachInst _machInst,
82 const char * instMnem, uint64_t setFlags,
83 InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest,
84 uint8_t _dataSize, int8_t _spm);
85
86 %(BasicExecDeclare)s
87 };
88}};
89
90def template MicroFpOpConstructor {{
| 1// Copyright (c) 2007 The Hewlett-Packard Development Company
2// Copyright (c) 2012-2013 Mark D. Hill and David A. Wood
3// All rights reserved.
4//
5// The license below extends only to copyright in the software and shall
6// not be construed as granting a license to any other intellectual
7// property including but not limited to intellectual property relating
8// to a hardware implementation of the functionality of the software
9// licensed hereunder. You may use the software subject to the license
10// terms below provided that you ensure that this notice is replicated
11// unmodified and in its entirety in all distributions of the software,
12// modified or unmodified, in source code or in binary form.
13//
14// Redistribution and use in source and binary forms, with or without
15// modification, are permitted provided that the following conditions are
16// met: redistributions of source code must retain the above copyright
17// notice, this list of conditions and the following disclaimer;
18// redistributions in binary form must reproduce the above copyright
19// notice, this list of conditions and the following disclaimer in the
20// documentation and/or other materials provided with the distribution;
21// neither the name of the copyright holders nor the names of its
22// contributors may be used to endorse or promote products derived from
23// this software without specific prior written permission.
24//
25// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36//
37// Authors: Gabe Black
38// Nilay Vaish
39
40//////////////////////////////////////////////////////////////////////////
41//
42// FpOp Microop templates
43//
44//////////////////////////////////////////////////////////////////////////
45
46def template MicroFpOpExecute {{
47 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
48 Trace::InstRecord *traceData) const
49 {
50 Fault fault = NoFault;
51
52 DPRINTF(X86, "The data size is %d\n", dataSize);
53 %(op_decl)s;
54 %(op_rd)s;
55
56 if(%(cond_check)s)
57 {
58 %(code)s;
59 %(flag_code)s;
60 %(tag_code)s;
61 %(top_code)s;
62 }
63 else
64 {
65 %(else_code)s;
66 }
67
68 //Write the resulting state to the execution context
69 if(fault == NoFault)
70 {
71 %(op_wb)s;
72 }
73 return fault;
74 }
75}};
76
77def template MicroFpOpDeclare {{
78 class %(class_name)s : public %(base_class)s
79 {
80 public:
81 %(class_name)s(ExtMachInst _machInst,
82 const char * instMnem, uint64_t setFlags,
83 InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest,
84 uint8_t _dataSize, int8_t _spm);
85
86 %(BasicExecDeclare)s
87 };
88}};
89
90def template MicroFpOpConstructor {{
|
92 ExtMachInst machInst, const char * instMnem, uint64_t setFlags,
93 InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest,
94 uint8_t _dataSize, int8_t _spm) :
95 %(base_class)s(machInst, "%(mnemonic)s", instMnem, setFlags,
96 _src1, _src2, _dest, _dataSize, _spm,
97 %(op_class)s)
98 {
99 %(constructor)s;
100 }
101}};
102
103let {{
104 # Make these empty strings so that concatenating onto
105 # them will always work.
106 header_output = ""
107 decoder_output = ""
108 exec_output = ""
109
110 class FpOpMeta(type):
111 def buildCppClasses(self, name, Name, suffix, \
112 code, flag_code, cond_check, else_code, op_class):
113
114 # Globals to stick the output in
115 global header_output
116 global decoder_output
117 global exec_output
118
119 # Stick all the code together so it can be searched at once
120 allCode = "|".join((code, flag_code, cond_check, else_code))
121
122 # If there's something optional to do with flags, generate
123 # a version without it and fix up this version to use it.
124 if flag_code is not "" or cond_check is not "true":
125 self.buildCppClasses(name, Name, suffix,
126 code, "", "true", else_code, op_class)
127 suffix = "Flags" + suffix
128
129 base = "X86ISA::FpOp"
130
131 # Get everything ready for the substitution
132 iop_tag = InstObjParams(name, Name + suffix + "TopTag", base,
133 {"code" : code,
134 "flag_code" : flag_code,
135 "cond_check" : cond_check,
136 "else_code" : else_code,
137 "tag_code" : "FTW = genX87Tags(FTW, TOP, spm);",
138 "top_code" : "TOP = (TOP + spm + 8) % 8;",
139 "op_class" : op_class})
140 iop_top = InstObjParams(name, Name + suffix + "Top", base,
141 {"code" : code,
142 "flag_code" : flag_code,
143 "cond_check" : cond_check,
144 "else_code" : else_code,
145 "tag_code" : ";",
146 "top_code" : "TOP = (TOP + spm + 8) % 8;",
147 "op_class" : op_class})
148 iop = InstObjParams(name, Name + suffix, base,
149 {"code" : code,
150 "flag_code" : flag_code,
151 "cond_check" : cond_check,
152 "else_code" : else_code,
153 "tag_code" : ";",
154 "top_code" : ";",
155 "op_class" : op_class})
156
157 # Generate the actual code (finally!)
158 header_output += MicroFpOpDeclare.subst(iop_tag)
159 decoder_output += MicroFpOpConstructor.subst(iop_tag)
160 exec_output += MicroFpOpExecute.subst(iop_tag)
161 header_output += MicroFpOpDeclare.subst(iop_top)
162 decoder_output += MicroFpOpConstructor.subst(iop_top)
163 exec_output += MicroFpOpExecute.subst(iop_top)
164 header_output += MicroFpOpDeclare.subst(iop)
165 decoder_output += MicroFpOpConstructor.subst(iop)
166 exec_output += MicroFpOpExecute.subst(iop)
167
168
169 def __new__(mcls, Name, bases, dict):
170 abstract = False
171 name = Name.lower()
172 if "abstract" in dict:
173 abstract = dict['abstract']
174 del dict['abstract']
175
176 cls = super(FpOpMeta, mcls).__new__(mcls, Name, bases, dict)
177 if not abstract:
178 cls.className = Name
179 cls.mnemonic = name
180 code = cls.code
181 flag_code = cls.flag_code
182 cond_check = cls.cond_check
183 else_code = cls.else_code
184 op_class = cls.op_class
185
186 # Set up the C++ classes
187 mcls.buildCppClasses(cls, name, Name, "",
188 code, flag_code, cond_check, else_code, op_class)
189
190 # Hook into the microassembler dict
191 global microopClasses
192 microopClasses[name] = cls
193
194 return cls
195
196 class FpUnaryOp(X86Microop):
197 __metaclass__ = FpOpMeta
198 # This class itself doesn't act as a microop
199 abstract = True
200
201 # Default template parameter values
202 flag_code = ""
203 cond_check = "true"
204 else_code = ";"
205 op_class = "FloatAddOp"
206
207 def __init__(self, dest, src1, spm=0, \
208 SetStatus=False, UpdateFTW=True, dataSize="env.dataSize"):
209 self.dest = dest
210 self.src1 = src1
211 self.src2 = "InstRegIndex(0)"
212 self.spm = spm
213 self.dataSize = dataSize
214 if SetStatus:
215 self.className += "Flags"
216 if spm:
217 self.className += "Top"
218 if spm and UpdateFTW:
219 self.className += "Tag"
220
221 def getAllocator(self, microFlags):
222 return '''new %(class_name)s(machInst, macrocodeBlock,
223 %(flags)s, %(src1)s, %(src2)s, %(dest)s,
224 %(dataSize)s, %(spm)d)''' % {
225 "class_name" : self.className,
226 "flags" : self.microFlagsText(microFlags),
227 "src1" : self.src1, "src2" : self.src2,
228 "dest" : self.dest,
229 "dataSize" : self.dataSize,
230 "spm" : self.spm}
231
232 class FpBinaryOp(X86Microop):
233 __metaclass__ = FpOpMeta
234 # This class itself doesn't act as a microop
235 abstract = True
236
237 # Default template parameter values
238 flag_code = ""
239 cond_check = "true"
240 else_code = ";"
241 op_class = "FloatAddOp"
242
243 def __init__(self, dest, src1, src2, spm=0, \
244 SetStatus=False, UpdateFTW=True, dataSize="env.dataSize"):
245 self.dest = dest
246 self.src1 = src1
247 self.src2 = src2
248 self.spm = spm
249 self.dataSize = dataSize
250 if SetStatus:
251 self.className += "Flags"
252 if spm:
253 self.className += "Top"
254 if spm and UpdateFTW:
255 self.className += "Tag"
256
257 def getAllocator(self, microFlags):
258 return '''new %(class_name)s(machInst, macrocodeBlock,
259 %(flags)s, %(src1)s, %(src2)s, %(dest)s,
260 %(dataSize)s, %(spm)d)''' % {
261 "class_name" : self.className,
262 "flags" : self.microFlagsText(microFlags),
263 "src1" : self.src1, "src2" : self.src2,
264 "dest" : self.dest,
265 "dataSize" : self.dataSize,
266 "spm" : self.spm}
267
268 class Movfp(FpUnaryOp):
269 code = 'FpDestReg_uqw = FpSrcReg1_uqw;'
270 else_code = 'FpDestReg_uqw = FpDestReg_uqw;'
271 cond_check = "checkCondition(ccFlagBits | cfofBits | dfBit | \
272 ecfBit | ezfBit, src2)"
273
274 class Xorfp(FpBinaryOp):
275 code = 'FpDestReg_uqw = FpSrcReg1_uqw ^ FpSrcReg2_uqw;'
276
277 class Sqrtfp(FpBinaryOp):
278 code = 'FpDestReg = sqrt(FpSrcReg2);'
279 op_class = 'FloatSqrtOp'
280
281 class Cosfp(FpUnaryOp):
282 code = 'FpDestReg = cos(FpSrcReg1);'
283 op_class = 'FloatSqrtOp'
284
285 class Sinfp(FpUnaryOp):
286 code = 'FpDestReg = sin(FpSrcReg1);'
287 op_class = 'FloatSqrtOp'
288
289 class Tanfp(FpUnaryOp):
290 code = 'FpDestReg = tan(FpSrcReg1);'
291 op_class = 'FloatSqrtOp'
292
293
294 # Conversion microops
295 class ConvOp(FpBinaryOp):
296 abstract = True
297 op_class = 'FloatCvtOp'
298 def __init__(self, dest, src1, **kwargs):
299 super(ConvOp, self).__init__(dest, src1, \
300 "InstRegIndex(FLOATREG_MICROFP0)", \
301 **kwargs)
302
303 # These probably shouldn't look at the ExtMachInst directly to figure
304 # out what size to use and should instead delegate that to the macroop's
305 # constructor. That would be more efficient, and it would make the
306 # microops a little more modular.
307 class cvtf_i2d(ConvOp):
308 code = '''
309 X86IntReg intReg = SSrcReg1;
310 if (REX_W)
311 FpDestReg = intReg.SR;
312 else
313 FpDestReg = intReg.SE;
314 '''
315
316 class cvtf_i2d_hi(ConvOp):
317 code = 'FpDestReg = bits(SSrcReg1, 63, 32);'
318
319 class cvtf_d2i(ConvOp):
320 code = '''
321 int64_t intSrcReg1 = static_cast<int64_t>(FpSrcReg1);
322 if (REX_W)
323 SDestReg = intSrcReg1;
324 else
325 SDestReg = merge(SDestReg, intSrcReg1, 4);
326 '''
327
328 # Convert two integers registers representing an 80-bit floating
329 # point number to an x87 register.
330 class cvtint_fp80(FpBinaryOp):
331 code = '''
332 uint8_t bits[10];
333 *(uint64_t *)(bits + 0) = SSrcReg1;
334 *(uint16_t *)(bits + 8) = (uint16_t)SSrcReg2;
335 FpDestReg = loadFloat80(bits);
336 '''
337
338 # Convert an x87 register (double) into extended precision and
339 # extract the highest 64 bits.
340 class cvtfp80h_int(ConvOp):
341 code = '''
342 char bits[10];
343 storeFloat80(bits, FpSrcReg1);
344 SDestReg = *(uint64_t *)(bits + 0);
345 '''
346
347 # Convert an x87 register (double) into extended precision and
348 # extract the lowest 16 bits.
349 class cvtfp80l_int(ConvOp):
350 code = '''
351 char bits[10];
352 storeFloat80(bits, FpSrcReg1);
353 SDestReg = *(uint16_t *)(bits + 8);
354 '''
355
356 # These need to consider size at some point. They'll always use doubles
357 # for the moment.
358 class addfp(FpBinaryOp):
359 code = 'FpDestReg = FpSrcReg1 + FpSrcReg2;'
360
361 class mulfp(FpBinaryOp):
362 code = 'FpDestReg = FpSrcReg1 * FpSrcReg2;'
363 op_class = 'FloatMultOp'
364
365 class divfp(FpBinaryOp):
366 code = 'FpDestReg = FpSrcReg1 / FpSrcReg2;'
367 op_class = 'FloatDivOp'
368
369 class subfp(FpBinaryOp):
370 code = 'FpDestReg = FpSrcReg1 - FpSrcReg2;'
371
372 class Yl2xFp(FpBinaryOp):
373 code = '''
374 FpDestReg = FpSrcReg2 * (log(FpSrcReg1) / log(2));
375 '''
376 op_class = 'FloatSqrtOp'
377
378 class PremFp(FpBinaryOp):
379 code = '''
380 MiscReg new_fsw(FSW);
381 int src1_exp;
382 int src2_exp;
383 std::frexp(FpSrcReg1, &src1_exp);
384 std::frexp(FpSrcReg2, &src2_exp);
385
386 const int d(src2_exp - src1_exp);
387 if (d < 64) {
388 const int64_t q(std::trunc(FpSrcReg2 / FpSrcReg1));
389 FpDestReg = FpSrcReg2 - FpSrcReg1 * q;
390 new_fsw &= ~(CC0Bit | CC1Bit | CC2Bit | CC2Bit);
391 new_fsw |= (q & 0x1) ? CC1Bit : 0;
392 new_fsw |= (q & 0x2) ? CC3Bit : 0;
393 new_fsw |= (q & 0x4) ? CC0Bit : 0;
394 } else {
395 const int n(42);
396 const int64_t qq(std::trunc(
397 FpSrcReg2 / std::ldexp(FpSrcReg1, d - n)));
398 FpDestReg = FpSrcReg2 - std::ldexp(FpSrcReg1 * qq, d - n);
399 new_fsw |= CC2Bit;
400 }
401 DPRINTF(X86, "src1: %lf, src2: %lf, dest: %lf, FSW: 0x%x\\n",
402 FpSrcReg1, FpSrcReg2, FpDestReg, new_fsw);
403 '''
404 op_class = 'FloatDivOp'
405
406 flag_code = 'FSW = new_fsw;'
407
408 class Compfp(FpBinaryOp):
409 def __init__(self, src1, src2, spm=0, setStatus=False, updateFTW=True, \
410 dataSize="env.dataSize"):
411 super(Compfp, self).__init__("InstRegIndex(FLOATREG_MICROFP0)", \
412 src1, src2, spm, setStatus, updateFTW, dataSize)
413 # This class sets the condition codes in rflags according to the
414 # rules for comparing floating point.
415 code = '''
416 // ZF PF CF
417 // Unordered 1 1 1
418 // Greater than 0 0 0
419 // Less than 0 0 1
420 // Equal 1 0 0
421 // OF = SF = AF = 0
422 ccFlagBits = ccFlagBits & ~(SFBit | AFBit | ZFBit | PFBit);
423 cfofBits = cfofBits & ~(OFBit | CFBit);
424
425 if (std::isnan(FpSrcReg1) || std::isnan(FpSrcReg2)) {
426 ccFlagBits = ccFlagBits | (ZFBit | PFBit);
427 cfofBits = cfofBits | CFBit;
428 }
429 else if(FpSrcReg1 < FpSrcReg2)
430 cfofBits = cfofBits | CFBit;
431 else if(FpSrcReg1 == FpSrcReg2)
432 ccFlagBits = ccFlagBits | ZFBit;
433 '''
434 op_class = 'FloatCmpOp'
435
436 class absfp(FpUnaryOp):
437 code = 'FpDestReg = fabs(FpSrcReg1);'
438 flag_code = 'FSW = FSW & (~CC1Bit);'
439
440 class chsfp(FpUnaryOp):
441 code = 'FpDestReg = (-1) * (FpSrcReg1);'
442 flag_code = 'FSW = FSW & (~CC1Bit);'
443
444 class Pop87(FpUnaryOp):
445 def __init__(self, spm=1, UpdateFTW=True):
446 super(Pop87, self).__init__( \
447 "InstRegIndex(FLOATREG_MICROFP0)", \
448 "InstRegIndex(FLOATREG_MICROFP0)", \
449 spm=spm, SetStatus=False, UpdateFTW=UpdateFTW)
450
451 code = ''
452}};
| 92 ExtMachInst machInst, const char * instMnem, uint64_t setFlags,
93 InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest,
94 uint8_t _dataSize, int8_t _spm) :
95 %(base_class)s(machInst, "%(mnemonic)s", instMnem, setFlags,
96 _src1, _src2, _dest, _dataSize, _spm,
97 %(op_class)s)
98 {
99 %(constructor)s;
100 }
101}};
102
103let {{
104 # Make these empty strings so that concatenating onto
105 # them will always work.
106 header_output = ""
107 decoder_output = ""
108 exec_output = ""
109
110 class FpOpMeta(type):
111 def buildCppClasses(self, name, Name, suffix, \
112 code, flag_code, cond_check, else_code, op_class):
113
114 # Globals to stick the output in
115 global header_output
116 global decoder_output
117 global exec_output
118
119 # Stick all the code together so it can be searched at once
120 allCode = "|".join((code, flag_code, cond_check, else_code))
121
122 # If there's something optional to do with flags, generate
123 # a version without it and fix up this version to use it.
124 if flag_code is not "" or cond_check is not "true":
125 self.buildCppClasses(name, Name, suffix,
126 code, "", "true", else_code, op_class)
127 suffix = "Flags" + suffix
128
129 base = "X86ISA::FpOp"
130
131 # Get everything ready for the substitution
132 iop_tag = InstObjParams(name, Name + suffix + "TopTag", base,
133 {"code" : code,
134 "flag_code" : flag_code,
135 "cond_check" : cond_check,
136 "else_code" : else_code,
137 "tag_code" : "FTW = genX87Tags(FTW, TOP, spm);",
138 "top_code" : "TOP = (TOP + spm + 8) % 8;",
139 "op_class" : op_class})
140 iop_top = InstObjParams(name, Name + suffix + "Top", base,
141 {"code" : code,
142 "flag_code" : flag_code,
143 "cond_check" : cond_check,
144 "else_code" : else_code,
145 "tag_code" : ";",
146 "top_code" : "TOP = (TOP + spm + 8) % 8;",
147 "op_class" : op_class})
148 iop = InstObjParams(name, Name + suffix, base,
149 {"code" : code,
150 "flag_code" : flag_code,
151 "cond_check" : cond_check,
152 "else_code" : else_code,
153 "tag_code" : ";",
154 "top_code" : ";",
155 "op_class" : op_class})
156
157 # Generate the actual code (finally!)
158 header_output += MicroFpOpDeclare.subst(iop_tag)
159 decoder_output += MicroFpOpConstructor.subst(iop_tag)
160 exec_output += MicroFpOpExecute.subst(iop_tag)
161 header_output += MicroFpOpDeclare.subst(iop_top)
162 decoder_output += MicroFpOpConstructor.subst(iop_top)
163 exec_output += MicroFpOpExecute.subst(iop_top)
164 header_output += MicroFpOpDeclare.subst(iop)
165 decoder_output += MicroFpOpConstructor.subst(iop)
166 exec_output += MicroFpOpExecute.subst(iop)
167
168
169 def __new__(mcls, Name, bases, dict):
170 abstract = False
171 name = Name.lower()
172 if "abstract" in dict:
173 abstract = dict['abstract']
174 del dict['abstract']
175
176 cls = super(FpOpMeta, mcls).__new__(mcls, Name, bases, dict)
177 if not abstract:
178 cls.className = Name
179 cls.mnemonic = name
180 code = cls.code
181 flag_code = cls.flag_code
182 cond_check = cls.cond_check
183 else_code = cls.else_code
184 op_class = cls.op_class
185
186 # Set up the C++ classes
187 mcls.buildCppClasses(cls, name, Name, "",
188 code, flag_code, cond_check, else_code, op_class)
189
190 # Hook into the microassembler dict
191 global microopClasses
192 microopClasses[name] = cls
193
194 return cls
195
196 class FpUnaryOp(X86Microop):
197 __metaclass__ = FpOpMeta
198 # This class itself doesn't act as a microop
199 abstract = True
200
201 # Default template parameter values
202 flag_code = ""
203 cond_check = "true"
204 else_code = ";"
205 op_class = "FloatAddOp"
206
207 def __init__(self, dest, src1, spm=0, \
208 SetStatus=False, UpdateFTW=True, dataSize="env.dataSize"):
209 self.dest = dest
210 self.src1 = src1
211 self.src2 = "InstRegIndex(0)"
212 self.spm = spm
213 self.dataSize = dataSize
214 if SetStatus:
215 self.className += "Flags"
216 if spm:
217 self.className += "Top"
218 if spm and UpdateFTW:
219 self.className += "Tag"
220
221 def getAllocator(self, microFlags):
222 return '''new %(class_name)s(machInst, macrocodeBlock,
223 %(flags)s, %(src1)s, %(src2)s, %(dest)s,
224 %(dataSize)s, %(spm)d)''' % {
225 "class_name" : self.className,
226 "flags" : self.microFlagsText(microFlags),
227 "src1" : self.src1, "src2" : self.src2,
228 "dest" : self.dest,
229 "dataSize" : self.dataSize,
230 "spm" : self.spm}
231
232 class FpBinaryOp(X86Microop):
233 __metaclass__ = FpOpMeta
234 # This class itself doesn't act as a microop
235 abstract = True
236
237 # Default template parameter values
238 flag_code = ""
239 cond_check = "true"
240 else_code = ";"
241 op_class = "FloatAddOp"
242
243 def __init__(self, dest, src1, src2, spm=0, \
244 SetStatus=False, UpdateFTW=True, dataSize="env.dataSize"):
245 self.dest = dest
246 self.src1 = src1
247 self.src2 = src2
248 self.spm = spm
249 self.dataSize = dataSize
250 if SetStatus:
251 self.className += "Flags"
252 if spm:
253 self.className += "Top"
254 if spm and UpdateFTW:
255 self.className += "Tag"
256
257 def getAllocator(self, microFlags):
258 return '''new %(class_name)s(machInst, macrocodeBlock,
259 %(flags)s, %(src1)s, %(src2)s, %(dest)s,
260 %(dataSize)s, %(spm)d)''' % {
261 "class_name" : self.className,
262 "flags" : self.microFlagsText(microFlags),
263 "src1" : self.src1, "src2" : self.src2,
264 "dest" : self.dest,
265 "dataSize" : self.dataSize,
266 "spm" : self.spm}
267
268 class Movfp(FpUnaryOp):
269 code = 'FpDestReg_uqw = FpSrcReg1_uqw;'
270 else_code = 'FpDestReg_uqw = FpDestReg_uqw;'
271 cond_check = "checkCondition(ccFlagBits | cfofBits | dfBit | \
272 ecfBit | ezfBit, src2)"
273
274 class Xorfp(FpBinaryOp):
275 code = 'FpDestReg_uqw = FpSrcReg1_uqw ^ FpSrcReg2_uqw;'
276
277 class Sqrtfp(FpBinaryOp):
278 code = 'FpDestReg = sqrt(FpSrcReg2);'
279 op_class = 'FloatSqrtOp'
280
281 class Cosfp(FpUnaryOp):
282 code = 'FpDestReg = cos(FpSrcReg1);'
283 op_class = 'FloatSqrtOp'
284
285 class Sinfp(FpUnaryOp):
286 code = 'FpDestReg = sin(FpSrcReg1);'
287 op_class = 'FloatSqrtOp'
288
289 class Tanfp(FpUnaryOp):
290 code = 'FpDestReg = tan(FpSrcReg1);'
291 op_class = 'FloatSqrtOp'
292
293
294 # Conversion microops
295 class ConvOp(FpBinaryOp):
296 abstract = True
297 op_class = 'FloatCvtOp'
298 def __init__(self, dest, src1, **kwargs):
299 super(ConvOp, self).__init__(dest, src1, \
300 "InstRegIndex(FLOATREG_MICROFP0)", \
301 **kwargs)
302
303 # These probably shouldn't look at the ExtMachInst directly to figure
304 # out what size to use and should instead delegate that to the macroop's
305 # constructor. That would be more efficient, and it would make the
306 # microops a little more modular.
307 class cvtf_i2d(ConvOp):
308 code = '''
309 X86IntReg intReg = SSrcReg1;
310 if (REX_W)
311 FpDestReg = intReg.SR;
312 else
313 FpDestReg = intReg.SE;
314 '''
315
316 class cvtf_i2d_hi(ConvOp):
317 code = 'FpDestReg = bits(SSrcReg1, 63, 32);'
318
319 class cvtf_d2i(ConvOp):
320 code = '''
321 int64_t intSrcReg1 = static_cast<int64_t>(FpSrcReg1);
322 if (REX_W)
323 SDestReg = intSrcReg1;
324 else
325 SDestReg = merge(SDestReg, intSrcReg1, 4);
326 '''
327
328 # Convert two integers registers representing an 80-bit floating
329 # point number to an x87 register.
330 class cvtint_fp80(FpBinaryOp):
331 code = '''
332 uint8_t bits[10];
333 *(uint64_t *)(bits + 0) = SSrcReg1;
334 *(uint16_t *)(bits + 8) = (uint16_t)SSrcReg2;
335 FpDestReg = loadFloat80(bits);
336 '''
337
338 # Convert an x87 register (double) into extended precision and
339 # extract the highest 64 bits.
340 class cvtfp80h_int(ConvOp):
341 code = '''
342 char bits[10];
343 storeFloat80(bits, FpSrcReg1);
344 SDestReg = *(uint64_t *)(bits + 0);
345 '''
346
347 # Convert an x87 register (double) into extended precision and
348 # extract the lowest 16 bits.
349 class cvtfp80l_int(ConvOp):
350 code = '''
351 char bits[10];
352 storeFloat80(bits, FpSrcReg1);
353 SDestReg = *(uint16_t *)(bits + 8);
354 '''
355
356 # These need to consider size at some point. They'll always use doubles
357 # for the moment.
358 class addfp(FpBinaryOp):
359 code = 'FpDestReg = FpSrcReg1 + FpSrcReg2;'
360
361 class mulfp(FpBinaryOp):
362 code = 'FpDestReg = FpSrcReg1 * FpSrcReg2;'
363 op_class = 'FloatMultOp'
364
365 class divfp(FpBinaryOp):
366 code = 'FpDestReg = FpSrcReg1 / FpSrcReg2;'
367 op_class = 'FloatDivOp'
368
369 class subfp(FpBinaryOp):
370 code = 'FpDestReg = FpSrcReg1 - FpSrcReg2;'
371
372 class Yl2xFp(FpBinaryOp):
373 code = '''
374 FpDestReg = FpSrcReg2 * (log(FpSrcReg1) / log(2));
375 '''
376 op_class = 'FloatSqrtOp'
377
378 class PremFp(FpBinaryOp):
379 code = '''
380 MiscReg new_fsw(FSW);
381 int src1_exp;
382 int src2_exp;
383 std::frexp(FpSrcReg1, &src1_exp);
384 std::frexp(FpSrcReg2, &src2_exp);
385
386 const int d(src2_exp - src1_exp);
387 if (d < 64) {
388 const int64_t q(std::trunc(FpSrcReg2 / FpSrcReg1));
389 FpDestReg = FpSrcReg2 - FpSrcReg1 * q;
390 new_fsw &= ~(CC0Bit | CC1Bit | CC2Bit | CC2Bit);
391 new_fsw |= (q & 0x1) ? CC1Bit : 0;
392 new_fsw |= (q & 0x2) ? CC3Bit : 0;
393 new_fsw |= (q & 0x4) ? CC0Bit : 0;
394 } else {
395 const int n(42);
396 const int64_t qq(std::trunc(
397 FpSrcReg2 / std::ldexp(FpSrcReg1, d - n)));
398 FpDestReg = FpSrcReg2 - std::ldexp(FpSrcReg1 * qq, d - n);
399 new_fsw |= CC2Bit;
400 }
401 DPRINTF(X86, "src1: %lf, src2: %lf, dest: %lf, FSW: 0x%x\\n",
402 FpSrcReg1, FpSrcReg2, FpDestReg, new_fsw);
403 '''
404 op_class = 'FloatDivOp'
405
406 flag_code = 'FSW = new_fsw;'
407
408 class Compfp(FpBinaryOp):
409 def __init__(self, src1, src2, spm=0, setStatus=False, updateFTW=True, \
410 dataSize="env.dataSize"):
411 super(Compfp, self).__init__("InstRegIndex(FLOATREG_MICROFP0)", \
412 src1, src2, spm, setStatus, updateFTW, dataSize)
413 # This class sets the condition codes in rflags according to the
414 # rules for comparing floating point.
415 code = '''
416 // ZF PF CF
417 // Unordered 1 1 1
418 // Greater than 0 0 0
419 // Less than 0 0 1
420 // Equal 1 0 0
421 // OF = SF = AF = 0
422 ccFlagBits = ccFlagBits & ~(SFBit | AFBit | ZFBit | PFBit);
423 cfofBits = cfofBits & ~(OFBit | CFBit);
424
425 if (std::isnan(FpSrcReg1) || std::isnan(FpSrcReg2)) {
426 ccFlagBits = ccFlagBits | (ZFBit | PFBit);
427 cfofBits = cfofBits | CFBit;
428 }
429 else if(FpSrcReg1 < FpSrcReg2)
430 cfofBits = cfofBits | CFBit;
431 else if(FpSrcReg1 == FpSrcReg2)
432 ccFlagBits = ccFlagBits | ZFBit;
433 '''
434 op_class = 'FloatCmpOp'
435
436 class absfp(FpUnaryOp):
437 code = 'FpDestReg = fabs(FpSrcReg1);'
438 flag_code = 'FSW = FSW & (~CC1Bit);'
439
440 class chsfp(FpUnaryOp):
441 code = 'FpDestReg = (-1) * (FpSrcReg1);'
442 flag_code = 'FSW = FSW & (~CC1Bit);'
443
444 class Pop87(FpUnaryOp):
445 def __init__(self, spm=1, UpdateFTW=True):
446 super(Pop87, self).__init__( \
447 "InstRegIndex(FLOATREG_MICROFP0)", \
448 "InstRegIndex(FLOATREG_MICROFP0)", \
449 spm=spm, SetStatus=False, UpdateFTW=UpdateFTW)
450
451 code = ''
452}};
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