macroop.isa (4567:5c7b9832235d) macroop.isa (4587:2c9a2534a489)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 The Hewlett-Packard Development Company
4// All rights reserved.
5//
6// Redistribution and use of this software in source and binary forms,
7// with or without modification, are permitted provided that the
8// following conditions are met:

--- 175 unchanged lines hidden (view full) ---

184 return MacroConstructor.subst(iop);
185}};
186
187output header {{
188 struct EmulEnv
189 {
190 X86ISA::RegIndex reg;
191 X86ISA::RegIndex regm;
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 The Hewlett-Packard Development Company
4// All rights reserved.
5//
6// Redistribution and use of this software in source and binary forms,
7// with or without modification, are permitted provided that the
8// following conditions are met:

--- 175 unchanged lines hidden (view full) ---

184 return MacroConstructor.subst(iop);
185}};
186
187output header {{
188 struct EmulEnv
189 {
190 X86ISA::RegIndex reg;
191 X86ISA::RegIndex regm;
192 uint64_t immediate;
193 uint64_t displacement;
194 int addressSize;
192 uint8_t scale;
193 X86ISA::RegIndex index;
194 X86ISA::RegIndex base;
195 int dataSize;
195 int dataSize;
196 int addressSize;
197 int stackSize;
196
197 EmulEnv(X86ISA::RegIndex _reg, X86ISA::RegIndex _regm,
198
199 EmulEnv(X86ISA::RegIndex _reg, X86ISA::RegIndex _regm,
198 uint64_t _immediate, uint64_t _displacement,
199 int _addressSize, int _dataSize) :
200 int _dataSize, int _addressSize, int _stackSize) :
200 reg(_reg), regm(_regm),
201 reg(_reg), regm(_regm),
201 immediate(_immediate), displacement(_displacement),
202 addressSize(_addressSize), dataSize(_dataSize)
202 dataSize(_dataSize), addressSize(_addressSize),
203 stackSize(_stackSize)
203 {;}
204 };
205}};
206
207let {{
208 class EmulEnv(object):
209 def __init__(self):
210 self.reg = "0"
211 self.regUsed = False
212 self.regm = "0"
213 self.regmUsed = False
204 {;}
205 };
206}};
207
208let {{
209 class EmulEnv(object):
210 def __init__(self):
211 self.reg = "0"
212 self.regUsed = False
213 self.regm = "0"
214 self.regmUsed = False
214 self.immediate = "IMMEDIATE"
215 self.displacement = "DISPLACEMENT"
216 self.addressSize = "ADDRSIZE"
217 self.dataSize = "OPSIZE"
215 self.addressSize = "ADDRSIZE"
216 self.dataSize = "OPSIZE"
217 self.stackSize = "STACKSIZE"
218 def getAllocator(self):
219 return '''EmulEnv(%(reg)s,
220 %(regm)s,
218 def getAllocator(self):
219 return '''EmulEnv(%(reg)s,
220 %(regm)s,
221 %(immediate)s,
222 %(displacement)s,
221 %(dataSize)s,
223 %(addressSize)s,
222 %(addressSize)s,
224 %(dataSize)s)''' % \
223 %(stackSize)s)''' % \
225 self.__dict__
226 def addReg(self, reg):
227 if not self.regUsed:
228 self.reg = reg
229 self.regUsed = True
230 elif not self.regmUsed:
231 self.regm = reg
232 self.regmUsed = True

--- 17 unchanged lines hidden --- 		224 self.__dict__
225 def addReg(self, reg):
226 if not self.regUsed:
227 self.reg = reg
228 self.regUsed = True
229 elif not self.regmUsed:
230 self.regm = reg
231 self.regmUsed = True

--- 17 unchanged lines hidden ---