msrs.py (5409:0343cd06df4f) msrs.py (5418:501cb81c89df)
1# Copyright (c) 2008 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 70 unchanged lines hidden (view full) ---

79# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
80# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
81#
82# Authors: Gabe Black
83
84microcode = '''
85def macroop RDMSR
86{
1# Copyright (c) 2008 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 70 unchanged lines hidden (view full) ---

79# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
80# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
81#
82# Authors: Gabe Black
83
84microcode = '''
85def macroop RDMSR
86{
87 limm t1, "IntAddrPrefixMSR >> 3"
88 ld t2, intseg, [8, t1, rcx], dataSize=8, addressSize=4
87 ld t2, intseg, [8, rcx, t0], "IntAddrPrefixMSR << 3", \
88 dataSize=8, addressSize=4
89 mov rax, rax, t2, dataSize=4
90 srli t2, t2, 32, dataSize=8
91 mov rdx, rdx, t2, dataSize=4
92};
93
94def macroop WRMSR
95{
89 mov rax, rax, t2, dataSize=4
90 srli t2, t2, 32, dataSize=8
91 mov rdx, rdx, t2, dataSize=4
92};
93
94def macroop WRMSR
95{
96 limm t1, "IntAddrPrefixMSR >> 3"
97 mov t2, t2, rax, dataSize=4
98 slli t3, rdx, 32, dataSize=8
99 or t2, t2, t3, dataSize=8
96 mov t2, t2, rax, dataSize=4
97 slli t3, rdx, 32, dataSize=8
98 or t2, t2, t3, dataSize=8
100 st t2, intseg, [8, t1, rcx], dataSize=8, addressSize=4
99 st t2, intseg, [8, rcx, t0], "IntAddrPrefixMSR << 3", \
100 dataSize=8, addressSize=4
101};
102
103def macroop RDTSC
104{
105 rdtsc t1
106 mov rax, rax, t1, dataSize=4
107 srli t1, t1, 32, dataSize=8
108 mov rdx, rdx, t1, dataSize=4
109};
110'''
101};
102
103def macroop RDTSC
104{
105 rdtsc t1
106 mov rax, rax, t1, dataSize=4
107 srli t1, t1, 32, dataSize=8
108 mov rdx, rdx, t1, dataSize=4
109};
110'''