control_registers.py (6054:0aa0a6189767) control_registers.py (6055:40bdbc32e3db)
1# Copyright (c) 2009 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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63 # This logic sets MP, EM, and TS to whatever is in the operand. It will
64 # set PE but not clear it.
65 limm t2, "~ULL(0xe)", dataSize=8
66 and t1, t1, t2, dataSize=8
67 andi t2, t3, 0xf, dataSize=8
68 or t1, t1, t2, dataSize=8
69 wrcr 0, t1, dataSize=8
70};
1# Copyright (c) 2009 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 54 unchanged lines hidden (view full) ---

63 # This logic sets MP, EM, and TS to whatever is in the operand. It will
64 # set PE but not clear it.
65 limm t2, "~ULL(0xe)", dataSize=8
66 and t1, t1, t2, dataSize=8
67 andi t2, t3, 0xf, dataSize=8
68 or t1, t1, t2, dataSize=8
69 wrcr 0, t1, dataSize=8
70};
71
72def macroop SMSW_R {
73 rdcr reg, 0
74};
75
76def macroop SMSW_M {
77 rdcr t1, 0
78 st t1, seg, sib, disp, dataSize=2
79};
80
81def macroop SMSW_P {
82 rdcr t1, 0
83 rdip t7, dataSize=asz
84 st t1, seg, riprel, disp, dataSize=2
85};
71'''
86'''