romutil.py (6222:9ee4a06a960b) | romutil.py (11320:42ecb523c64a) |
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1# Copyright (c) 2008 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 52 unchanged lines hidden (view full) --- 61%(startLabel)s_processDescriptor: 62 chks t10, t3, IntCSCheck, dataSize=8 63 wrdl hs, t3, t10, dataSize=8 64 65 # Stick the target offset in t9. 66 wrdh t9, t4, t2, dataSize=8 67 68 | 1# Copyright (c) 2008 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 52 unchanged lines hidden (view full) --- 61%(startLabel)s_processDescriptor: 62 chks t10, t3, IntCSCheck, dataSize=8 63 wrdl hs, t3, t10, dataSize=8 64 65 # Stick the target offset in t9. 66 wrdh t9, t4, t2, dataSize=8 67 68 |
69 # | 69 # |
70 # Figure out where the stack should be 71 # 72 73 # Record what we might set the stack selector to. 74 rdsel t11, ss 75 76 # Check if we're changing privelege level. At this point we can assume | 70 # Figure out where the stack should be 71 # 72 73 # Record what we might set the stack selector to. 74 rdsel t11, ss 75 76 # Check if we're changing privelege level. At this point we can assume |
77 # we're going to a DPL that's less than or equal to the CPL. | 77 # we're going to a DPL that's less than or equal to the CPL. |
78 rdattr t10, hs, dataSize=8 79 andi t10, t10, 3, dataSize=8 80 rdattr t5, cs, dataSize=8 81 andi t5, t5, 0x3, dataSize=8 82 sub t0, t5, t10, flags=(EZF,), dataSize=8 83 # We're going to change priviledge, so zero out the stack selector. We 84 # need to let the IST have priority so we don't branch yet. 85 mov t11, t0, t0, flags=(nCEZF,) --- 48 unchanged lines hidden (view full) --- 134 ldst t0, hs, [1, t0, t6], \ 135 32 + %(errorCodeSize)d, dataSize=8, addressSize=8 136 137 138 # 139 # Build up the interrupt stack frame 140 # 141 | 78 rdattr t10, hs, dataSize=8 79 andi t10, t10, 3, dataSize=8 80 rdattr t5, cs, dataSize=8 81 andi t5, t5, 0x3, dataSize=8 82 sub t0, t5, t10, flags=(EZF,), dataSize=8 83 # We're going to change priviledge, so zero out the stack selector. We 84 # need to let the IST have priority so we don't branch yet. 85 mov t11, t0, t0, flags=(nCEZF,) --- 48 unchanged lines hidden (view full) --- 134 ldst t0, hs, [1, t0, t6], \ 135 32 + %(errorCodeSize)d, dataSize=8, addressSize=8 136 137 138 # 139 # Build up the interrupt stack frame 140 # 141 |
142 | 142 |
143 # Write out the contents of memory 144 %(errorCodeCode)s 145 st t7, hs, [1, t0, t6], %(errorCodeSize)d, dataSize=8, addressSize=8 146 st t10, hs, [1, t0, t6], 8 + %(errorCodeSize)d, dataSize=8, addressSize=8 147 rflags t10, dataSize=8 148 st t10, hs, [1, t0, t6], 16 + %(errorCodeSize)d, dataSize=8, addressSize=8 149 st rsp, hs, [1, t0, t6], 24 + %(errorCodeSize)d, dataSize=8, addressSize=8 150 rdsel t5, ss, dataSize=2 --- 17 unchanged lines hidden (view full) --- 168 srli t7, t10, 9, dataSize=8 169 xor t5, t7, t5, dataSize=8 170 andi t5, t5, 1, dataSize=8 171 slli t5, t5, 9, dataSize=8 172 or t6, t5, t6, dataSize=8 173 174 # Put the results into rflags 175 wrflags t6, t10 | 143 # Write out the contents of memory 144 %(errorCodeCode)s 145 st t7, hs, [1, t0, t6], %(errorCodeSize)d, dataSize=8, addressSize=8 146 st t10, hs, [1, t0, t6], 8 + %(errorCodeSize)d, dataSize=8, addressSize=8 147 rflags t10, dataSize=8 148 st t10, hs, [1, t0, t6], 16 + %(errorCodeSize)d, dataSize=8, addressSize=8 149 st rsp, hs, [1, t0, t6], 24 + %(errorCodeSize)d, dataSize=8, addressSize=8 150 rdsel t5, ss, dataSize=2 --- 17 unchanged lines hidden (view full) --- 168 srli t7, t10, 9, dataSize=8 169 xor t5, t7, t5, dataSize=8 170 andi t5, t5, 1, dataSize=8 171 slli t5, t5, 9, dataSize=8 172 or t6, t5, t6, dataSize=8 173 174 # Put the results into rflags 175 wrflags t6, t10 |
176 | 176 |
177 eret 178}; 179''' 180 181microcode = \ 182intCodeTemplate % {\ 183 "startLabel" : "longModeInterrupt", 184 "gateCheckType" : "IntGateCheck", --- 37 unchanged lines hidden --- | 177 eret 178}; 179''' 180 181microcode = \ 182intCodeTemplate % {\ 183 "startLabel" : "longModeInterrupt", 184 "gateCheckType" : "IntGateCheck", --- 37 unchanged lines hidden --- |