romutil.py (5911:8d6e40f38063) romutil.py (5913:f2bfe08dc873)
1# Copyright (c) 2008 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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35 extern %(startLabel)s:
36
37 #
38 # Get the 64 bit interrupt or trap gate descriptor from the IDT
39 #
40
41 # Load the gate descriptor from the IDT
42 slli t4, t1, 4, dataSize=8
1# Copyright (c) 2008 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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35 extern %(startLabel)s:
36
37 #
38 # Get the 64 bit interrupt or trap gate descriptor from the IDT
39 #
40
41 # Load the gate descriptor from the IDT
42 slli t4, t1, 4, dataSize=8
43 ld t2, idtr, [1, t0, t4], 8, dataSize=8, addressSize=8
44 ld t4, idtr, [1, t0, t4], dataSize=8, addressSize=8
43 ld t2, idtr, [1, t0, t4], 8, dataSize=8, addressSize=8, atCPL0=True
44 ld t4, idtr, [1, t0, t4], dataSize=8, addressSize=8, atCPL0=True
45
46 # Make sure the descriptor is a legal gate.
47 chks t1, t4, %(gateCheckType)s
48
49 #
50 # Get the target CS descriptor using the selector in the gate
51 # descriptor.
52 #
53 srli t10, t4, 16, dataSize=8
54 andi t5, t10, 0xF8, dataSize=8
55 andi t0, t10, 0x4, flags=(EZF,), dataSize=2
56 br rom_local_label("%(startLabel)s_globalDescriptor"), flags=(CEZF,)
45
46 # Make sure the descriptor is a legal gate.
47 chks t1, t4, %(gateCheckType)s
48
49 #
50 # Get the target CS descriptor using the selector in the gate
51 # descriptor.
52 #
53 srli t10, t4, 16, dataSize=8
54 andi t5, t10, 0xF8, dataSize=8
55 andi t0, t10, 0x4, flags=(EZF,), dataSize=2
56 br rom_local_label("%(startLabel)s_globalDescriptor"), flags=(CEZF,)
57 ld t3, tsl, [1, t0, t5], dataSize=8, addressSize=8
57 ld t3, tsl, [1, t0, t5], dataSize=8, addressSize=8, atCPL0=True
58 br rom_local_label("%(startLabel)s_processDescriptor")
59%(startLabel)s_globalDescriptor:
58 br rom_local_label("%(startLabel)s_processDescriptor")
59%(startLabel)s_globalDescriptor:
60 ld t3, tsg, [1, t0, t5], dataSize=8, addressSize=8
60 ld t3, tsg, [1, t0, t5], dataSize=8, addressSize=8, atCPL0=True
61%(startLabel)s_processDescriptor:
62 chks t10, t3, IntCSCheck, dataSize=8
63 wrdl hs, t3, t10, dataSize=8
64
65 # Stick the target offset in t9.
66 wrdh t9, t4, t2, dataSize=8
67
68

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99 br rom_local_label("%(startLabel)s_stackSwitched")
100
101%(startLabel)s_istStackSwitch:
102 panic "IST based stack switching isn't implemented"
103 br rom_local_label("%(startLabel)s_stackSwitched")
104
105%(startLabel)s_cplStackSwitch:
106 # Get the new rsp from the TSS
61%(startLabel)s_processDescriptor:
62 chks t10, t3, IntCSCheck, dataSize=8
63 wrdl hs, t3, t10, dataSize=8
64
65 # Stick the target offset in t9.
66 wrdh t9, t4, t2, dataSize=8
67
68

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99 br rom_local_label("%(startLabel)s_stackSwitched")
100
101%(startLabel)s_istStackSwitch:
102 panic "IST based stack switching isn't implemented"
103 br rom_local_label("%(startLabel)s_stackSwitched")
104
105%(startLabel)s_cplStackSwitch:
106 # Get the new rsp from the TSS
107 ld t6, tr, [8, t10, t0], 4, dataSize=8, addressSize=8
107 ld t6, tr, [8, t10, t0], 4, dataSize=8, addressSize=8, atCPL0=True
108
109%(startLabel)s_stackSwitched:
110
111 andi t6, t6, 0xF0, dataSize=1
112 subi t6, t6, 40 + %(errorCodeSize)d, dataSize=8
113
108
109%(startLabel)s_stackSwitched:
110
111 andi t6, t6, 0xF0, dataSize=1
112 subi t6, t6, 40 + %(errorCodeSize)d, dataSize=8
113
114 # Check that we can access everything we need to on the stack
115 ldst t0, hs, [1, t0, t6], dataSize=8, addressSize=8
116 ldst t0, hs, [1, t0, t6], \
117 32 + %(errorCodeSize)d, dataSize=8, addressSize=8
118
119 ##
120 ## Point of no return.
121 ## We're now going to irrevocably modify visible state.
122 ## Anything bad that's going to happen should have happened by now or will
123 ## happen right now.
124 ##
125 wrip t0, t9, dataSize=8
126

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131 srli t5, t4, 16, dataSize=8
132 andi t5, t5, 0xFF, dataSize=8
133 wrdl cs, t3, t5, dataSize=8
134 # Tuck away the old CS for use below
135 limm t10, 0, dataSize=8
136 rdsel t10, cs, dataSize=2
137 wrsel cs, t5, dataSize=2
138
114 ##
115 ## Point of no return.
116 ## We're now going to irrevocably modify visible state.
117 ## Anything bad that's going to happen should have happened by now or will
118 ## happen right now.
119 ##
120 wrip t0, t9, dataSize=8
121

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126 srli t5, t4, 16, dataSize=8
127 andi t5, t5, 0xFF, dataSize=8
128 wrdl cs, t3, t5, dataSize=8
129 # Tuck away the old CS for use below
130 limm t10, 0, dataSize=8
131 rdsel t10, cs, dataSize=2
132 wrsel cs, t5, dataSize=2
133
134 # Check that we can access everything we need to on the stack
135 ldst t0, hs, [1, t0, t6], dataSize=8, addressSize=8
136 ldst t0, hs, [1, t0, t6], \
137 32 + %(errorCodeSize)d, dataSize=8, addressSize=8
139
138
139
140 #
141 # Build up the interrupt stack frame
142 #
143
144
145 # Write out the contents of memory
146 %(errorCodeCode)s
147 st t7, hs, [1, t0, t6], %(errorCodeSize)d, dataSize=8, addressSize=8

--- 65 unchanged lines hidden --- 		140 #
141 # Build up the interrupt stack frame
142 #
143
144
145 # Write out the contents of memory
146 %(errorCodeCode)s
147 st t7, hs, [1, t0, t6], %(errorCodeSize)d, dataSize=8, addressSize=8

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