romutil.py (5858:54f64fb1bd62) romutil.py (5903:3d7f94358641)
1# Copyright (c) 2008 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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75
76 # Check if we're changing privelege level. At this point we can assume
77 # we're going to a DPL that's less than or equal to the CPL.
78 rdattr t10, hs, dataSize=8
79 srli t10, t10, 3, dataSize=8
80 andi t10, t10, 3, dataSize=8
81 rdattr t5, cs, dataSize=8
82 srli t5, t5, 3, dataSize=8
1# Copyright (c) 2008 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 66 unchanged lines hidden (view full) ---

75
76 # Check if we're changing privelege level. At this point we can assume
77 # we're going to a DPL that's less than or equal to the CPL.
78 rdattr t10, hs, dataSize=8
79 srli t10, t10, 3, dataSize=8
80 andi t10, t10, 3, dataSize=8
81 rdattr t5, cs, dataSize=8
82 srli t5, t5, 3, dataSize=8
83 sub t5, t5, t10, dataSize=8
84 andi t0, t5, 0x3, flags=(EZF,), dataSize=8
83 andi t5, t5, 0x3, dataSize=8
84 sub t0, t5, t10, flags=(EZF,), dataSize=8
85 # We're going to change priviledge, so zero out the stack selector. We
86 # need to let the IST have priority so we don't branch yet.
87 wrsel t11, t0, flags=(nCEZF,)
88
89 # Check the IST field of the gate descriptor
85 # We're going to change priviledge, so zero out the stack selector. We
86 # need to let the IST have priority so we don't branch yet.
87 wrsel t11, t0, flags=(nCEZF,)
88
89 # Check the IST field of the gate descriptor
90 srli t10, t4, 32, dataSize=8
91 andi t10, t10, 0x7, dataSize=8
92 subi t0, t10, 1, flags=(ECF,), dataSize=8
90 srli t12, t4, 32, dataSize=8
91 andi t12, t12, 0x7, dataSize=8
92 subi t0, t12, 1, flags=(ECF,), dataSize=8
93 br rom_local_label("%(startLabel)s_istStackSwitch"), flags=(nCECF,)
94 br rom_local_label("%(startLabel)s_cplStackSwitch"), flags=(nCEZF,)
95
96 # If we're here, it's because the stack isn't being switched.
97 # Set t6 to the new aligned rsp.
98 mov t6, t6, rsp, dataSize=8
93 br rom_local_label("%(startLabel)s_istStackSwitch"), flags=(nCECF,)
94 br rom_local_label("%(startLabel)s_cplStackSwitch"), flags=(nCEZF,)
95
96 # If we're here, it's because the stack isn't being switched.
97 # Set t6 to the new aligned rsp.
98 mov t6, t6, rsp, dataSize=8
99 andi t6, t6, 0xF0, dataSize=1
100 subi t6, t6, 40 + %(errorCodeSize)d, dataSize=8
101
102 # Check that we can access everything we need to on the stack
103 ldst t0, hs, [1, t0, t6], dataSize=8, addressSize=8
104 ldst t0, hs, [1, t0, t6], \
105 32 + %(errorCodeSize)d, dataSize=8, addressSize=8
106 br rom_local_label("%(startLabel)s_stackSwitched")
107
108%(startLabel)s_istStackSwitch:
109 panic "IST based stack switching isn't implemented"
110 br rom_local_label("%(startLabel)s_stackSwitched")
111
112%(startLabel)s_cplStackSwitch:
99 br rom_local_label("%(startLabel)s_stackSwitched")
100
101%(startLabel)s_istStackSwitch:
102 panic "IST based stack switching isn't implemented"
103 br rom_local_label("%(startLabel)s_stackSwitched")
104
105%(startLabel)s_cplStackSwitch:
113 panic "CPL change initiated stack switching isn't implemented"
106 # Get the new rsp from the TSS
107 ld t6, tr, [8, t10, t0], 4, dataSize=8, addressSize=8
114
115%(startLabel)s_stackSwitched:
116
108
109%(startLabel)s_stackSwitched:
110
111 andi t6, t6, 0xF0, dataSize=1
112 subi t6, t6, 40 + %(errorCodeSize)d, dataSize=8
117
113
114 # Check that we can access everything we need to on the stack
115 ldst t0, hs, [1, t0, t6], dataSize=8, addressSize=8
116 ldst t0, hs, [1, t0, t6], \
117 32 + %(errorCodeSize)d, dataSize=8, addressSize=8
118
118 ##
119 ## Point of no return.
120 ## We're now going to irrevocably modify visible state.
121 ## Anything bad that's going to happen should have happened by now or will
122 ## happen right now.
123 ##
124 wrip t0, t9, dataSize=8
125

--- 84 unchanged lines hidden --- 		119 ##
120 ## Point of no return.
121 ## We're now going to irrevocably modify visible state.
122 ## Anything bad that's going to happen should have happened by now or will
123 ## happen right now.
124 ##
125 wrip t0, t9, dataSize=8
126

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