romutil.py (5680:39ae093fb4eb) romutil.py (5852:1a40b07bbc30)
1# Copyright (c) 2008 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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54 xori t4, t4, 0xe, flags=(EZF,), dataSize=8
55 fault "new GeneralProtection(0)", flags=(nCEZF,)
56
57
58 #
59 # Get the target CS descriptor using the selector in the gate
60 # descriptor.
61 #
1# Copyright (c) 2008 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 45 unchanged lines hidden (view full) ---

54 xori t4, t4, 0xe, flags=(EZF,), dataSize=8
55 fault "new GeneralProtection(0)", flags=(nCEZF,)
56
57
58 #
59 # Get the target CS descriptor using the selector in the gate
60 # descriptor.
61 #
62 srli t4, t1, 16, dataSize=8
63 andi t5, t4, 0xF8, dataSize=8
64 andi t0, t4, 0x4, flags=(EZF,), dataSize=2
62 srli t10, t4, 16, dataSize=8
63 andi t5, t10, 0xF8, dataSize=8
64 andi t0, t10, 0x4, flags=(EZF,), dataSize=2
65 br rom_local_label("globalDescriptor"), flags=(CEZF,)
66 ld t3, tsl, [1, t0, t5], dataSize=8, addressSize=8
67 br rom_local_label("processDescriptor")
68globalDescriptor:
69 ld t3, tsg, [1, t0, t5], dataSize=8, addressSize=8
70processDescriptor:
65 br rom_local_label("globalDescriptor"), flags=(CEZF,)
66 ld t3, tsl, [1, t0, t5], dataSize=8, addressSize=8
67 br rom_local_label("processDescriptor")
68globalDescriptor:
69 ld t3, tsg, [1, t0, t5], dataSize=8, addressSize=8
70processDescriptor:
71 chks t4, t3, IntCSCheck, dataSize=8
72 wrdl hs, t3, t4, dataSize=8
71 chks t10, t3, IntCSCheck, dataSize=8
72 wrdl hs, t3, t10, dataSize=8
73
73
74 # Check that the target offset is in canonical form
75 wrdh t4, t1, t2, dataSize=8
76 srli t4, t4, 47, dataSize=8
77 addi t4, t4, 1, dataSize=8
78 srli t4, t4, 1, dataSize=8
79 or t4, t4, t4, flags=(EZF,), dataSize=2
80 fault "new GeneralProtection(0)", flags=(nCEZF,)
74 # Stick the target offset in t9.
75 wrdh t9, t4, t2, dataSize=8
81
82
83 #
84 # Figure out where the stack should be
85 #
86
87 # Record what we might set the stack selector to.
76
77
78 #
79 # Figure out where the stack should be
80 #
81
82 # Record what we might set the stack selector to.
88 rdsel t6, ss
89 wrsel hs, t6
83 rdsel t11, ss
90
91 # Check if we're changing privelege level. At this point we can assume
92 # we're going to a DPL that's less than or equal to the CPL.
84
85 # Check if we're changing privelege level. At this point we can assume
86 # we're going to a DPL that's less than or equal to the CPL.
93 rdattr t4, hs, dataSize=8
94 srli t4, t4, 3, dataSize=8
95 andi t4, t4, 3, dataSize=8
87 rdattr t10, hs, dataSize=8
88 srli t10, t10, 3, dataSize=8
89 andi t10, t10, 3, dataSize=8
96 rdattr t5, cs, dataSize=8
97 srli t5, t5, 3, dataSize=8
90 rdattr t5, cs, dataSize=8
91 srli t5, t5, 3, dataSize=8
98 sub t5, t5, t4, dataSize=8
92 sub t5, t5, t10, dataSize=8
99 andi t0, t5, 0x3, flags=(EZF,), dataSize=8
100 # We're going to change priviledge, so zero out the stack selector. We
101 # need to let the IST have priority so we don't branch yet.
93 andi t0, t5, 0x3, flags=(EZF,), dataSize=8
94 # We're going to change priviledge, so zero out the stack selector. We
95 # need to let the IST have priority so we don't branch yet.
102 limm t4, 0
103 wrsel hs, t4, flags=(nCEZF,)
96 wrsel t11, t0, flags=(nCEZF,)
104
105 # Check the IST field of the gate descriptor
97
98 # Check the IST field of the gate descriptor
106 srli t4, t1, 32, dataSize=8
107 andi t4, t4, 0x7, dataSize=8
108 subi t0, t4, 1, flags=(ECF,), dataSize=8
99 srli t10, t4, 32, dataSize=8
100 andi t10, t10, 0x7, dataSize=8
101 subi t0, t10, 1, flags=(ECF,), dataSize=8
109 br rom_local_label("istStackSwitch"), flags=(nCECF,)
110 br rom_local_label("cplStackSwitch"), flags=(nCEZF,)
111
112 # If we're here, it's because the stack isn't being switched.
113 # Set t6 to the new rsp.
114 subi t6, rsp, 40, dataSize=8
115
116 # Align the stack

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129 panic "CPL change initiated stack switching isn't implemented"
130
131stackSwitched:
132
133
134 ##
135 ## Point of no return.
136 ## We're now going to irrevocably modify visible state.
102 br rom_local_label("istStackSwitch"), flags=(nCECF,)
103 br rom_local_label("cplStackSwitch"), flags=(nCEZF,)
104
105 # If we're here, it's because the stack isn't being switched.
106 # Set t6 to the new rsp.
107 subi t6, rsp, 40, dataSize=8
108
109 # Align the stack

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122 panic "CPL change initiated stack switching isn't implemented"
123
124stackSwitched:
125
126
127 ##
128 ## Point of no return.
129 ## We're now going to irrevocably modify visible state.
137 ## Anything bad that's going to happen should have happened by now.
130 ## Anything bad that's going to happen should have happened by now or will
131 ## happen right now.
138 ##
132 ##
133 wrip t0, t9, dataSize=8
139
140
141 #
142 # Build up the interrupt stack frame
143 #
144
134
135
136 #
137 # Build up the interrupt stack frame
138 #
139
140
145 # Write out the contents of memory
146 st t7, hs, [1, t0, t6], dataSize=8
147 limm t5, 0, dataSize=8
148 rdsel t5, cs, dataSize=2
149 st t5, hs, [1, t0, t6], 8, dataSize=8
141 # Write out the contents of memory
142 st t7, hs, [1, t0, t6], dataSize=8
143 limm t5, 0, dataSize=8
144 rdsel t5, cs, dataSize=2
145 st t5, hs, [1, t0, t6], 8, dataSize=8
150 rflags t4, dataSize=8
151 st t4, hs, [1, t0, t6], 16, dataSize=8
146 rflags t10, dataSize=8
147 st t10, hs, [1, t0, t6], 16, dataSize=8
152 st rsp, hs, [1, t0, t6], 24, dataSize=8
153 rdsel t5, ss, dataSize=2
154 st t5, hs, [1, t0, t6], 32, dataSize=8
155
156 # Set the stack segment
157 mov rsp, rsp, t6, dataSize=8
148 st rsp, hs, [1, t0, t6], 24, dataSize=8
149 rdsel t5, ss, dataSize=2
150 st t5, hs, [1, t0, t6], 32, dataSize=8
151
152 # Set the stack segment
153 mov rsp, rsp, t6, dataSize=8
158 rdsel t7, hs, dataSize=2
159 wrsel ss, t7, dataSize=2
154 wrsel ss, t11, dataSize=2
160
161 #
162 # Set up the target code segment
163 #
155
156 #
157 # Set up the target code segment
158 #
164 srli t5, t1, 16, dataSize=8
159 srli t5, t4, 16, dataSize=8
165 andi t5, t5, 0xFF, dataSize=8
166 wrdl cs, t3, t5, dataSize=8
167 wrsel cs, t5, dataSize=2
160 andi t5, t5, 0xFF, dataSize=8
161 wrdl cs, t3, t5, dataSize=8
162 wrsel cs, t5, dataSize=2
168 wrdh t7, t1, t2, dataSize=8
169 wrip t0, t7, dataSize=8
170
171 #
163
164 #
172 # Adjust rflags which is still in t4 from above
165 # Adjust rflags which is still in t10 from above
173 #
174
175 # Set IF to the lowest bit of the original gate type.
176 # The type field of the original gate starts at bit 40.
177
178 # Set the TF, NT, and RF bits. We'll flip them at the end.
179 limm t6, (1 << 8) | (1 << 14) | (1 << 16)
166 #
167
168 # Set IF to the lowest bit of the original gate type.
169 # The type field of the original gate starts at bit 40.
170
171 # Set the TF, NT, and RF bits. We'll flip them at the end.
172 limm t6, (1 << 8) | (1 << 14) | (1 << 16)
180 or t4, t4, t6
181 srli t5, t1, 40, dataSize=8
182 srli t7, t4, 9, dataSize=8
173 or t10, t10, t6
174 srli t5, t4, 40, dataSize=8
175 srli t7, t10, 9, dataSize=8
183 xor t5, t7, t5, dataSize=8
184 andi t5, t5, 1, dataSize=8
185 slli t5, t5, 9, dataSize=8
186 or t6, t5, t6, dataSize=8
187
188 # Put the results into rflags
176 xor t5, t7, t5, dataSize=8
177 andi t5, t5, 1, dataSize=8
178 slli t5, t5, 9, dataSize=8
179 or t6, t5, t6, dataSize=8
180
181 # Put the results into rflags
189 wrflags t6, t4
182 wrflags t6, t10
190
191 eret
192};
193
194def rom
195{
196 # This vectors the CPU into an interrupt handler in legacy mode.
197 extern legacyModeInterrupt:
198 panic "Legacy mode interrupts not implemented (in microcode)"
199 eret
200};
201'''
183
184 eret
185};
186
187def rom
188{
189 # This vectors the CPU into an interrupt handler in legacy mode.
190 extern legacyModeInterrupt:
191 panic "Legacy mode interrupts not implemented (in microcode)"
192 eret
193};
194'''