semaphores.py (8610:9bdd52a2214c) semaphores.py (11329:82bb3ee706b3)
1# Copyright (c) 2007 The Hewlett-Packard Development Company
1# Copyright (c) 2007 The Hewlett-Packard Development Company
2# Copyright (c) 2015 Advanced Micro Devices, Inc.
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Redistribution and use in source and binary forms, with or without
14# modification, are permitted provided that the following conditions are
15# met: redistributions of source code must retain the above copyright
16# notice, this list of conditions and the following disclaimer;
17# redistributions in binary form must reproduce the above copyright
18# notice, this list of conditions and the following disclaimer in the
19# documentation and/or other materials provided with the distribution;
20# neither the name of the copyright holders nor the names of its
21# contributors may be used to endorse or promote products derived from
22# this software without specific prior written permission.
23#
24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35#
36# Authors: Gabe Black
37
38microcode = '''
39def macroop CMPXCHG_R_R {
40 sub t0, rax, reg, flags=(OF, SF, ZF, AF, PF, CF)
41 mov reg, reg, regm, flags=(CZF,)
42 mov rax, rax, reg, flags=(nCZF,)
43};
44
45def macroop CMPXCHG_M_R {
46 ldst t1, seg, sib, disp
47 sub t0, rax, t1, flags=(OF, SF, ZF, AF, PF, CF)
48
49 mov t1, t1, reg, flags=(CZF,)
50 st t1, seg, sib, disp
51 mov rax, rax, t1, flags=(nCZF,)
52};
53
54def macroop CMPXCHG_P_R {
55 rdip t7
56 ldst t1, seg, riprel, disp
57 sub t0, rax, t1, flags=(OF, SF, ZF, AF, PF, CF)
58
59 mov t1, t1, reg, flags=(CZF,)
60 st t1, seg, riprel, disp
61 mov rax, rax, t1, flags=(nCZF,)
62};
63
64def macroop CMPXCHG_LOCKED_M_R {
65 mfence
66 ldstl t1, seg, sib, disp
67 sub t0, rax, t1, flags=(OF, SF, ZF, AF, PF, CF)
68
69 mov t1, t1, reg, flags=(CZF,)
70 stul t1, seg, sib, disp
71 mfence
72 mov rax, rax, t1, flags=(nCZF,)
73};
74
75def macroop CMPXCHG_LOCKED_P_R {
76 rdip t7
77 mfence
78 ldstl t1, seg, riprel, disp
79 sub t0, rax, t1, flags=(OF, SF, ZF, AF, PF, CF)
80
81 mov t1, t1, reg, flags=(CZF,)
82 stul t1, seg, riprel, disp
83 mfence
84 mov rax, rax, t1, flags=(nCZF,)
85};
86
87def macroop XADD_M_R {
88 ldst t1, seg, sib, disp
89 add t2, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
90 st t2, seg, sib, disp
91 mov reg, reg, t1
92};
93
94def macroop XADD_P_R {
95 rdip t7
96 ldst t1, seg, riprel, disp
97 add t2, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
98 st t2, seg, riprel, disp
99 mov reg, reg, t1
100};
101
102def macroop XADD_LOCKED_M_R {
103 mfence
104 ldstl t1, seg, sib, disp
105 add t2, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
106 stul t2, seg, sib, disp
107 mfence
108 mov reg, reg, t1
109};
110
111def macroop XADD_LOCKED_P_R {
112 rdip t7
113 mfence
114 ldstl t1, seg, riprel, disp
115 add t2, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
116 stul t2, seg, riprel, disp
117 mfence
118 mov reg, reg, t1
119};
120
121def macroop XADD_R_R {
122 add t2, regm, reg, flags=(OF,SF,ZF,AF,PF,CF)
123 mov regm, regm, reg
124 mov reg, reg, t2
125};
126
127'''
128
3# All rights reserved.
4#
5# The license below extends only to copyright in the software and shall
6# not be construed as granting a license to any other intellectual
7# property including but not limited to intellectual property relating
8# to a hardware implementation of the functionality of the software
9# licensed hereunder. You may use the software subject to the license
10# terms below provided that you ensure that this notice is replicated
11# unmodified and in its entirety in all distributions of the software,
12# modified or unmodified, in source code or in binary form.
13#
14# Redistribution and use in source and binary forms, with or without
15# modification, are permitted provided that the following conditions are
16# met: redistributions of source code must retain the above copyright
17# notice, this list of conditions and the following disclaimer;
18# redistributions in binary form must reproduce the above copyright
19# notice, this list of conditions and the following disclaimer in the
20# documentation and/or other materials provided with the distribution;
21# neither the name of the copyright holders nor the names of its
22# contributors may be used to endorse or promote products derived from
23# this software without specific prior written permission.
24#
25# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36#
37# Authors: Gabe Black
38
39microcode = '''
40def macroop CMPXCHG_R_R {
41 sub t0, rax, reg, flags=(OF, SF, ZF, AF, PF, CF)
42 mov reg, reg, regm, flags=(CZF,)
43 mov rax, rax, reg, flags=(nCZF,)
44};
45
46def macroop CMPXCHG_M_R {
47 ldst t1, seg, sib, disp
48 sub t0, rax, t1, flags=(OF, SF, ZF, AF, PF, CF)
49
50 mov t1, t1, reg, flags=(CZF,)
51 st t1, seg, sib, disp
52 mov rax, rax, t1, flags=(nCZF,)
53};
54
55def macroop CMPXCHG_P_R {
56 rdip t7
57 ldst t1, seg, riprel, disp
58 sub t0, rax, t1, flags=(OF, SF, ZF, AF, PF, CF)
59
60 mov t1, t1, reg, flags=(CZF,)
61 st t1, seg, riprel, disp
62 mov rax, rax, t1, flags=(nCZF,)
63};
64
65def macroop CMPXCHG_LOCKED_M_R {
66 mfence
67 ldstl t1, seg, sib, disp
68 sub t0, rax, t1, flags=(OF, SF, ZF, AF, PF, CF)
69
70 mov t1, t1, reg, flags=(CZF,)
71 stul t1, seg, sib, disp
72 mfence
73 mov rax, rax, t1, flags=(nCZF,)
74};
75
76def macroop CMPXCHG_LOCKED_P_R {
77 rdip t7
78 mfence
79 ldstl t1, seg, riprel, disp
80 sub t0, rax, t1, flags=(OF, SF, ZF, AF, PF, CF)
81
82 mov t1, t1, reg, flags=(CZF,)
83 stul t1, seg, riprel, disp
84 mfence
85 mov rax, rax, t1, flags=(nCZF,)
86};
87
88def macroop XADD_M_R {
89 ldst t1, seg, sib, disp
90 add t2, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
91 st t2, seg, sib, disp
92 mov reg, reg, t1
93};
94
95def macroop XADD_P_R {
96 rdip t7
97 ldst t1, seg, riprel, disp
98 add t2, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
99 st t2, seg, riprel, disp
100 mov reg, reg, t1
101};
102
103def macroop XADD_LOCKED_M_R {
104 mfence
105 ldstl t1, seg, sib, disp
106 add t2, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
107 stul t2, seg, sib, disp
108 mfence
109 mov reg, reg, t1
110};
111
112def macroop XADD_LOCKED_P_R {
113 rdip t7
114 mfence
115 ldstl t1, seg, riprel, disp
116 add t2, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
117 stul t2, seg, riprel, disp
118 mfence
119 mov reg, reg, t1
120};
121
122def macroop XADD_R_R {
123 add t2, regm, reg, flags=(OF,SF,ZF,AF,PF,CF)
124 mov regm, regm, reg
125 mov reg, reg, t2
126};
127
128'''
129
130# Despite the name, this microcode sequence implements both
131# cmpxchg8b and cmpxchg16b, depending on the dynamic value
132# of dataSize.
129cmpxchg8bCode = '''
130def macroop CMPXCHG8B_%(suffix)s {
131 %(rdip)s
132 lea t1, seg, %(sib)s, disp, dataSize=asz
133cmpxchg8bCode = '''
134def macroop CMPXCHG8B_%(suffix)s {
135 %(rdip)s
136 lea t1, seg, %(sib)s, disp, dataSize=asz
133 ldst%(l)s t2, seg, [1, t0, t1], 0
134 ldst%(l)s t3, seg, [1, t0, t1], dsz
137 ldsplit%(l)s (t2, t3), seg, [1, t0, t1], disp=0
135
136 sub t0, rax, t2, flags=(ZF,)
137 br label("doneComparing"), flags=(nCZF,)
138 sub t0, rdx, t3, flags=(ZF,)
139doneComparing:
140
141 # If they're equal, set t3:t2 to rbx:rcx to write to memory
142 mov t2, t2, rbx, flags=(CZF,)
143 mov t3, t3, rcx, flags=(CZF,)
144
145 # If they're not equal, set rdx:rax to the value from memory.
146 mov rax, rax, t2, flags=(nCZF,)
147 mov rdx, rdx, t3, flags=(nCZF,)
148
149 # Write to memory
138
139 sub t0, rax, t2, flags=(ZF,)
140 br label("doneComparing"), flags=(nCZF,)
141 sub t0, rdx, t3, flags=(ZF,)
142doneComparing:
143
144 # If they're equal, set t3:t2 to rbx:rcx to write to memory
145 mov t2, t2, rbx, flags=(CZF,)
146 mov t3, t3, rcx, flags=(CZF,)
147
148 # If they're not equal, set rdx:rax to the value from memory.
149 mov rax, rax, t2, flags=(nCZF,)
150 mov rdx, rdx, t3, flags=(nCZF,)
151
152 # Write to memory
150 st%(ul)s t3, seg, [1, t0, t1], dsz
151 st%(ul)s t2, seg, [1, t0, t1], 0
153 stsplit%(ul)s (t2, t3), seg, [1, t0, t1], disp=0
152};
153'''
154
155microcode += cmpxchg8bCode % {"rdip": "", "sib": "sib",
156 "l": "", "ul": "",
157 "suffix": "M"}
158microcode += cmpxchg8bCode % {"rdip": "rdip t7", "sib": "riprel",
159 "l": "", "ul": "",
160 "suffix": "P"}
161microcode += cmpxchg8bCode % {"rdip": "", "sib": "sib",
162 "l": "l", "ul": "ul",
163 "suffix": "LOCKED_M"}
164microcode += cmpxchg8bCode % {"rdip": "rdip t7", "sib": "riprel",
165 "l": "l", "ul": "ul",
166 "suffix": "LOCKED_P"}
167
168#let {{
169# class XCHG(Inst):
170# "GenFault ${new UnimpInstFault}"
171#}};
154};
155'''
156
157microcode += cmpxchg8bCode % {"rdip": "", "sib": "sib",
158 "l": "", "ul": "",
159 "suffix": "M"}
160microcode += cmpxchg8bCode % {"rdip": "rdip t7", "sib": "riprel",
161 "l": "", "ul": "",
162 "suffix": "P"}
163microcode += cmpxchg8bCode % {"rdip": "", "sib": "sib",
164 "l": "l", "ul": "ul",
165 "suffix": "LOCKED_M"}
166microcode += cmpxchg8bCode % {"rdip": "rdip t7", "sib": "riprel",
167 "l": "l", "ul": "ul",
168 "suffix": "LOCKED_P"}
169
170#let {{
171# class XCHG(Inst):
172# "GenFault ${new UnimpInstFault}"
173#}};