1# Copyright (c) 2007 The Hewlett-Packard Development Company
2# Copyright (c) 2015 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# The license below extends only to copyright in the software and shall
6# not be construed as granting a license to any other intellectual
7# property including but not limited to intellectual property relating
8# to a hardware implementation of the functionality of the software
9# licensed hereunder. You may use the software subject to the license
10# terms below provided that you ensure that this notice is replicated
11# unmodified and in its entirety in all distributions of the software,
12# modified or unmodified, in source code or in binary form.
13#
14# Redistribution and use in source and binary forms, with or without
15# modification, are permitted provided that the following conditions are
16# met: redistributions of source code must retain the above copyright
17# notice, this list of conditions and the following disclaimer;
18# redistributions in binary form must reproduce the above copyright
19# notice, this list of conditions and the following disclaimer in the
20# documentation and/or other materials provided with the distribution;
21# neither the name of the copyright holders nor the names of its
22# contributors may be used to endorse or promote products derived from
23# this software without specific prior written permission.
24#
25# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36#
37# Authors: Gabe Black
38
39microcode = '''
40def macroop CMPXCHG_R_R {
41 sub t0, rax, reg, flags=(OF, SF, ZF, AF, PF, CF)
42 mov reg, reg, regm, flags=(CZF,)
43 mov rax, rax, reg, flags=(nCZF,)
44};
45
46def macroop CMPXCHG_M_R {
47 ldst t1, seg, sib, disp
48 sub t0, rax, t1, flags=(OF, SF, ZF, AF, PF, CF)
49
50 mov t1, t1, reg, flags=(CZF,)
51 st t1, seg, sib, disp
52 mov rax, rax, t1, flags=(nCZF,)
53};
54
55def macroop CMPXCHG_P_R {
56 rdip t7
57 ldst t1, seg, riprel, disp
58 sub t0, rax, t1, flags=(OF, SF, ZF, AF, PF, CF)
59
60 mov t1, t1, reg, flags=(CZF,)
61 st t1, seg, riprel, disp
62 mov rax, rax, t1, flags=(nCZF,)
63};
64
65def macroop CMPXCHG_LOCKED_M_R {
66 mfence
67 ldstl t1, seg, sib, disp
68 sub t0, rax, t1, flags=(OF, SF, ZF, AF, PF, CF)
69
70 mov t1, t1, reg, flags=(CZF,)
71 stul t1, seg, sib, disp
72 mfence
73 mov rax, rax, t1, flags=(nCZF,)
74};
75
76def macroop CMPXCHG_LOCKED_P_R {
77 rdip t7
78 mfence
79 ldstl t1, seg, riprel, disp
80 sub t0, rax, t1, flags=(OF, SF, ZF, AF, PF, CF)
81
82 mov t1, t1, reg, flags=(CZF,)
83 stul t1, seg, riprel, disp
84 mfence
85 mov rax, rax, t1, flags=(nCZF,)
86};
87
88def macroop XADD_M_R {
89 ldst t1, seg, sib, disp
90 add t2, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
91 st t2, seg, sib, disp
92 mov reg, reg, t1
93};
94
95def macroop XADD_P_R {
96 rdip t7
97 ldst t1, seg, riprel, disp
98 add t2, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
99 st t2, seg, riprel, disp
100 mov reg, reg, t1
101};
102
103def macroop XADD_LOCKED_M_R {
104 mfence
105 ldstl t1, seg, sib, disp
106 add t2, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
107 stul t2, seg, sib, disp
108 mfence
109 mov reg, reg, t1
110};
111
112def macroop XADD_LOCKED_P_R {
113 rdip t7
114 mfence
115 ldstl t1, seg, riprel, disp
116 add t2, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
117 stul t2, seg, riprel, disp
118 mfence
119 mov reg, reg, t1
120};
121
122def macroop XADD_R_R {
123 add t2, regm, reg, flags=(OF,SF,ZF,AF,PF,CF)
124 mov regm, regm, reg
125 mov reg, reg, t2
126};
127
128'''
129
130# Despite the name, this microcode sequence implements both
131# cmpxchg8b and cmpxchg16b, depending on the dynamic value
132# of dataSize.
133cmpxchg8bCode = '''
134def macroop CMPXCHG8B_%(suffix)s {
135 %(rdip)s
136 lea t1, seg, %(sib)s, disp, dataSize=asz
137 ldsplit%(l)s (t2, t3), seg, [1, t0, t1], disp=0
138
139 sub t0, rax, t2, flags=(ZF,)
140 br label("doneComparing"), flags=(nCZF,)
141 sub t0, rdx, t3, flags=(ZF,)
142doneComparing:
143
144 # If they're equal, set t3:t2 to rbx:rcx to write to memory
145 mov t2, t2, rbx, flags=(CZF,)
146 mov t3, t3, rcx, flags=(CZF,)
147
148 # If they're not equal, set rdx:rax to the value from memory.
149 mov rax, rax, t2, flags=(nCZF,)
150 mov rdx, rdx, t3, flags=(nCZF,)
151
152 # Write to memory
153 stsplit%(ul)s (t2, t3), seg, [1, t0, t1], disp=0
154};
155'''
156
157microcode += cmpxchg8bCode % {"rdip": "", "sib": "sib",
158 "l": "", "ul": "",
159 "suffix": "M"}
160microcode += cmpxchg8bCode % {"rdip": "rdip t7", "sib": "riprel",
161 "l": "", "ul": "",
162 "suffix": "P"}
163microcode += cmpxchg8bCode % {"rdip": "", "sib": "sib",
164 "l": "l", "ul": "ul",
165 "suffix": "LOCKED_M"}
166microcode += cmpxchg8bCode % {"rdip": "rdip t7", "sib": "riprel",
167 "l": "l", "ul": "ul",
168 "suffix": "LOCKED_P"}
169
170#let {{
171# class XCHG(Inst):
172# "GenFault ${new UnimpInstFault}"
173#}};