general_io.py (8103:53c2d9b1c15d) general_io.py (8672:2c7ece076c8b)
1# Copyright (c) 2007-2008 The Hewlett-Packard Development Company
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

--- 28 unchanged lines hidden (view full) ---

37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Gabe Black
40
41microcode = '''
42 def macroop IN_R_I {
43 .adjust_imm trimImm(8)
44 limm t1, imm, dataSize=asz
1# Copyright (c) 2007-2008 The Hewlett-Packard Development Company
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

--- 28 unchanged lines hidden (view full) ---

37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Gabe Black
40
41microcode = '''
42 def macroop IN_R_I {
43 .adjust_imm trimImm(8)
44 limm t1, imm, dataSize=asz
45 mfence
45 ld reg, intseg, [1, t1, t0], "IntAddrPrefixIO << 3", addressSize=8, \
46 nonSpec=True
46 ld reg, intseg, [1, t1, t0], "IntAddrPrefixIO << 3", addressSize=8, \
47 nonSpec=True
48 mfence
47 };
48
49 def macroop IN_R_R {
50 zexti t2, regm, 15, dataSize=8
49 };
50
51 def macroop IN_R_R {
52 zexti t2, regm, 15, dataSize=8
53 mfence
51 ld reg, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8, \
52 nonSpec=True
54 ld reg, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8, \
55 nonSpec=True
56 mfence
53 };
54
55 def macroop OUT_I_R {
56 .adjust_imm trimImm(8)
57 limm t1, imm, dataSize=8
57 };
58
59 def macroop OUT_I_R {
60 .adjust_imm trimImm(8)
61 limm t1, imm, dataSize=8
62 mfence
58 st reg, intseg, [1, t1, t0], "IntAddrPrefixIO << 3", addressSize=8, \
59 nonSpec=True
63 st reg, intseg, [1, t1, t0], "IntAddrPrefixIO << 3", addressSize=8, \
64 nonSpec=True
65 mfence
60 };
61
62 def macroop OUT_R_R {
63 zexti t2, reg, 15, dataSize=8
66 };
67
68 def macroop OUT_R_R {
69 zexti t2, reg, 15, dataSize=8
70 mfence
64 st regm, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8, \
65 nonSpec=True
71 st regm, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8, \
72 nonSpec=True
73 mfence
66 };
67'''
74 };
75'''