general_io.py (5418:501cb81c89df) general_io.py (5927:5e3367b103da)
1# Copyright (c) 2008 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 75 unchanged lines hidden (view full) ---

84microcode = '''
85 def macroop IN_R_I {
86 .adjust_imm trimImm(8)
87 limm t1, imm, dataSize=asz
88 ld reg, intseg, [1, t1, t0], "IntAddrPrefixIO << 3", addressSize=4
89 };
90
91 def macroop IN_R_R {
1# Copyright (c) 2008 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 75 unchanged lines hidden (view full) ---

84microcode = '''
85 def macroop IN_R_I {
86 .adjust_imm trimImm(8)
87 limm t1, imm, dataSize=asz
88 ld reg, intseg, [1, t1, t0], "IntAddrPrefixIO << 3", addressSize=4
89 };
90
91 def macroop IN_R_R {
92 zexti t2, regm, 15, dataSize=2
92 zexti t2, regm, 15, dataSize=8
93 ld reg, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=4
94 };
95
96 def macroop OUT_I_R {
97 .adjust_imm trimImm(8)
98 limm t1, imm, dataSize=8
99 st reg, intseg, [1, t1, t0], "IntAddrPrefixIO << 3", addressSize=4
100 };
101
102 def macroop OUT_R_R {
93 ld reg, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=4
94 };
95
96 def macroop OUT_I_R {
97 .adjust_imm trimImm(8)
98 limm t1, imm, dataSize=8
99 st reg, intseg, [1, t1, t0], "IntAddrPrefixIO << 3", addressSize=4
100 };
101
102 def macroop OUT_R_R {
103 zexti t2, reg, 15, dataSize=2
103 zexti t2, reg, 15, dataSize=8
104 st regm, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=4
105 };
106'''
104 st regm, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=4
105 };
106'''