general_io.py (5322:db50c4044662) general_io.py (5418:501cb81c89df)
1# Copyright (c) 2008 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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79# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
80# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
81#
82# Authors: Gabe Black
83
84microcode = '''
85 def macroop IN_R_I {
86 .adjust_imm trimImm(8)
1# Copyright (c) 2008 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 70 unchanged lines hidden (view full) ---

79# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
80# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
81#
82# Authors: Gabe Black
83
84microcode = '''
85 def macroop IN_R_I {
86 .adjust_imm trimImm(8)
87 limm t1, "IntAddrPrefixIO", dataSize=8
88 ld reg, intseg, [1, t1, t0], imm, addressSize=8
87 limm t1, imm, dataSize=asz
88 ld reg, intseg, [1, t1, t0], "IntAddrPrefixIO << 3", addressSize=4
89 };
90
91 def macroop IN_R_R {
89 };
90
91 def macroop IN_R_R {
92 limm t1, "IntAddrPrefixIO", dataSize=8
93 zexti t2, regm, 15, dataSize=2
92 zexti t2, regm, 15, dataSize=2
94 ld reg, intseg, [1, t1, t2], addressSize=8
93 ld reg, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=4
95 };
96
97 def macroop OUT_I_R {
98 .adjust_imm trimImm(8)
94 };
95
96 def macroop OUT_I_R {
97 .adjust_imm trimImm(8)
99 limm t1, "IntAddrPrefixIO", dataSize=8
100 st reg, intseg, [1, t1, t0], imm, addressSize=8
98 limm t1, imm, dataSize=8
99 st reg, intseg, [1, t1, t0], "IntAddrPrefixIO << 3", addressSize=4
101 };
102
103 def macroop OUT_R_R {
100 };
101
102 def macroop OUT_R_R {
104 limm t1, "IntAddrPrefixIO", dataSize=8
105 zexti t2, reg, 15, dataSize=2
103 zexti t2, reg, 15, dataSize=2
106 st regm, intseg, [1, t1, t2], addressSize=8
104 st regm, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=4
107 };
108'''
105 };
106'''