general_io.py (5081:2ccce8600a9d) general_io.py (5161:e7334f2d7bef)
1# Copyright (c) 2007 The Hewlett-Packard Development Company
2# All rights reserved.
3#
4# Redistribution and use of this software in source and binary forms,
5# with or without modification, are permitted provided that the
6# following conditions are met:
7#
8# The software must be used only for Non-Commercial Use which means any

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48# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
49# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
50# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
51# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
52# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
53#
54# Authors: Gabe Black
55
1# Copyright (c) 2007 The Hewlett-Packard Development Company
2# All rights reserved.
3#
4# Redistribution and use of this software in source and binary forms,
5# with or without modification, are permitted provided that the
6# following conditions are met:
7#
8# The software must be used only for Non-Commercial Use which means any

--- 39 unchanged lines hidden (view full) ---

48# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
49# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
50# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
51# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
52# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
53#
54# Authors: Gabe Black
55
56microcode = ""
57#let {{
58# class IN(Inst):
59# "GenFault ${new UnimpInstFault}"
60# class OUT(Inst):
61# "GenFault ${new UnimpInstFault}"
62#}};
56microcode = '''
57 def macroop IN_R_I {
58 .adjust_imm trimImm(8)
59 limm t1, "IntAddrPrefixIO"
60 ld reg, intseg, [1, t1, t0], imm, addressSize=2
61 };
62
63 def macroop IN_R_R {
64 limm t1, "IntAddrPrefixIO"
65 zext t2, regm, 16, dataSize=2
66 ld reg, intseg, [1, t1, t2], addressSize=8
67 };
68
69 def macroop OUT_I_R {
70 .adjust_imm trimImm(8)
71 limm t1, "IntAddrPrefixIO"
72 st reg, intseg, [1, t1, t0], imm, addressSize=8
73 };
74
75 def macroop OUT_R_R {
76 limm t1, "IntAddrPrefixIO"
77 zext t2, reg, 16, dataSize=2
78 st regm, intseg, [1, t1, t2], addressSize=8
79 };
80'''