bit_test.py (5081:2ccce8600a9d) | bit_test.py (5240:6dc723c9c6a9) |
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1# Copyright (c) 2007 The Hewlett-Packard Development Company 2# All rights reserved. 3# 4# Redistribution and use of this software in source and binary forms, 5# with or without modification, are permitted provided that the 6# following conditions are met: 7# 8# The software must be used only for Non-Commercial Use which means any --- 39 unchanged lines hidden (view full) --- 48# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 49# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 50# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 51# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 52# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 53# 54# Authors: Gabe Black 55 | 1# Copyright (c) 2007 The Hewlett-Packard Development Company 2# All rights reserved. 3# 4# Redistribution and use of this software in source and binary forms, 5# with or without modification, are permitted provided that the 6# following conditions are met: 7# 8# The software must be used only for Non-Commercial Use which means any --- 39 unchanged lines hidden (view full) --- 48# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 49# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 50# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 51# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 52# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 53# 54# Authors: Gabe Black 55 |
56microcode = "" 57#let {{ 58# class BT(Inst): 59# "GenFault ${new UnimpInstFault}" 60# class BTC(Inst): 61# "GenFault ${new UnimpInstFault}" 62# class BTR(Inst): 63# "GenFault ${new UnimpInstFault}" 64# class BTS(Inst): 65# "GenFault ${new UnimpInstFault}" 66#}}; | 56microcode = ''' 57def macroop BT_R_I { 58 sexti t0, reg, imm, flags=(CF,) 59}; 60 61def macroop BT_M_I { 62 limm t1, imm 63 # This fudges just a tiny bit, but it's reasonable to expect the 64 # microcode generation logic to have the log of the various sizes 65 # floating around as well. 66 srai t2, t1, "(env.dataSize == 8) ? 3 : ((env.dataSize == 4) ? 2 : 1)" 67 add t2, t2, base 68 ld t1, seg, [scale, index, t2], disp 69 sexti t0, t1, imm, flags=(CF,) 70}; 71 72def macroop BT_P_I { 73 rdip t7 74 limm t1, imm 75 srai t2, t1, "(env.dataSize == 8) ? 3 : ((env.dataSize == 4) ? 2 : 1)" 76 ld t1, seg, [1, t2, t7] 77 sexti t0, t1, imm, flags=(CF,) 78}; 79 80def macroop BT_R_R { 81 sext t0, reg, regm, flags=(CF,) 82}; 83 84def macroop BT_M_R { 85 limm t1, imm 86 srai t2, t1, "(env.dataSize == 8) ? 3 : ((env.dataSize == 4) ? 2 : 1)" 87 add t2, t2, base 88 ld t1, seg, [scale, index, t2], disp 89 sext t0, t1, reg, flags=(CF,) 90}; 91 92def macroop BT_P_R { 93 rdip t7 94 limm t1, imm 95 srai t2, t1, "(env.dataSize == 8) ? 3 : ((env.dataSize == 4) ? 2 : 1)" 96 ld t1, seg, [1, t2, t7] 97 sext t0, t1, reg, flags=(CF,) 98}; 99 100def macroop BTC_R_I { 101 sexti t0, reg, imm, flags=(CF,) 102 limm t1, 1 103 roli t1, t1, imm 104 xor reg, reg, t1 105}; 106 107def macroop BTC_M_I { 108 limm t1, imm 109 # This fudges just a tiny bit, but it's reasonable to expect the 110 # microcode generation logic to have the log of the various sizes 111 # floating around as well. 112 srai t2, t1, "(env.dataSize == 8) ? 3 : ((env.dataSize == 4) ? 2 : 1)" 113 add t2, t2, base 114 limm t3, 1 115 roli t3, t3, imm 116 ldst t1, seg, [scale, index, t2], disp 117 sexti t0, t1, imm, flags=(CF,) 118 xor t1, t1, t3 119 st t1, seg, [scale, index, t2], disp 120}; 121 122def macroop BTC_P_I { 123 rdip t7 124 limm t1, imm 125 srai t2, t1, "(env.dataSize == 8) ? 3 : ((env.dataSize == 4) ? 2 : 1)" 126 limm t3, 1 127 roli t3, t3, imm 128 ldst t1, seg, [1, t2, t7] 129 sexti t0, t1, imm, flags=(CF,) 130 xor t1, t1, t3 131 st t1, seg, [scale, index, t2], disp 132}; 133 134def macroop BTC_R_R { 135 sext t0, reg, regm, flags=(CF,) 136 limm t1, 1 137 rol t1, t1, regm 138 xor reg, reg, t1 139}; 140 141def macroop BTC_M_R { 142 limm t1, imm 143 srai t2, t1, "(env.dataSize == 8) ? 3 : ((env.dataSize == 4) ? 2 : 1)" 144 add t2, t2, base 145 limm t3, 1 146 rol t3, t3, reg 147 ldst t1, seg, [scale, index, t2], disp 148 sext t0, t1, reg, flags=(CF,) 149 xor t1, t1, t3 150 st t1, seg, [scale, index, t2], disp 151}; 152 153def macroop BTC_P_R { 154 rdip t7 155 limm t1, imm 156 srai t2, t1, "(env.dataSize == 8) ? 3 : ((env.dataSize == 4) ? 2 : 1)" 157 limm t3, 1 158 rol t3, t3, reg 159 ldst t1, seg, [1, t2, t7] 160 sext t0, t1, reg, flags=(CF,) 161 xor t1, t1, t3 162 st t1, seg, [scale, index, t2], disp 163}; 164 165def macroop BTR_R_I { 166 sexti t0, reg, imm, flags=(CF,) 167 limm t1, "(uint64_t(-(2ULL)))" 168 roli t1, t1, imm 169 and reg, reg, t1 170}; 171 172def macroop BTR_M_I { 173 limm t1, imm 174 # This fudges just a tiny bit, but it's reasonable to expect the 175 # microcode generation logic to have the log of the various sizes 176 # floating around as well. 177 srai t2, t1, "(env.dataSize == 8) ? 3 : ((env.dataSize == 4) ? 2 : 1)" 178 add t2, t2, base 179 limm t3, "(uint64_t(-(2ULL)))" 180 roli t3, t3, imm 181 ldst t1, seg, [scale, index, t2], disp 182 sexti t0, t1, imm, flags=(CF,) 183 and t1, t1, t3 184 st t1, seg, [scale, index, t2], disp 185}; 186 187def macroop BTR_P_I { 188 rdip t7 189 limm t1, imm 190 srai t2, t1, "(env.dataSize == 8) ? 3 : ((env.dataSize == 4) ? 2 : 1)" 191 limm t3, "(uint64_t(-(2ULL)))" 192 roli t3, t3, imm 193 ldst t1, seg, [1, t2, t7] 194 sexti t0, t1, imm, flags=(CF,) 195 and t1, t1, t3 196 st t1, seg, [scale, index, t2], disp 197}; 198 199def macroop BTR_R_R { 200 sext t0, reg, regm, flags=(CF,) 201 limm t1, "(uint64_t(-(2ULL)))" 202 rol t1, t1, regm 203 and reg, reg, t1 204}; 205 206def macroop BTR_M_R { 207 limm t1, imm 208 srai t2, t1, "(env.dataSize == 8) ? 3 : ((env.dataSize == 4) ? 2 : 1)" 209 add t2, t2, base 210 limm t3, "(uint64_t(-(2ULL)))" 211 rol t3, t3, reg 212 ldst t1, seg, [scale, index, t2], disp 213 sext t0, t1, reg, flags=(CF,) 214 and t1, t1, t3 215 st t1, seg, [scale, index, t2], disp 216}; 217 218def macroop BTR_P_R { 219 rdip t7 220 limm t1, imm 221 srai t2, t1, "(env.dataSize == 8) ? 3 : ((env.dataSize == 4) ? 2 : 1)" 222 limm t3, "(uint64_t(-(2ULL)))" 223 rol t3, t3, reg 224 ldst t1, seg, [1, t2, t7] 225 sext t0, t1, reg, flags=(CF,) 226 and t1, t1, t3 227 st t1, seg, [scale, index, t2], disp 228}; 229 230def macroop BTS_R_I { 231 sexti t0, reg, imm, flags=(CF,) 232 limm t1, 1 233 roli t1, t1, imm 234 or reg, reg, t1 235}; 236 237def macroop BTS_M_I { 238 limm t1, imm 239 # This fudges just a tiny bit, but it's reasonable to expect the 240 # microcode generation logic to have the log of the various sizes 241 # floating around as well. 242 srai t2, t1, "(env.dataSize == 8) ? 3 : ((env.dataSize == 4) ? 2 : 1)" 243 add t2, t2, base 244 limm t3, 1 245 roli t3, t3, imm 246 ldst t1, seg, [scale, index, t2], disp 247 sexti t0, t1, imm, flags=(CF,) 248 or t1, t1, t3 249 st t1, seg, [scale, index, t2], disp 250}; 251 252def macroop BTS_P_I { 253 rdip t7 254 limm t1, imm 255 srai t2, t1, "(env.dataSize == 8) ? 3 : ((env.dataSize == 4) ? 2 : 1)" 256 limm t3, 1 257 roli t3, t3, imm 258 ldst t1, seg, [1, t2, t7] 259 sexti t0, t1, imm, flags=(CF,) 260 or t1, t1, t3 261 st t1, seg, [scale, index, t2], disp 262}; 263 264def macroop BTS_R_R { 265 sext t0, reg, regm, flags=(CF,) 266 limm t1, 1 267 rol t1, t1, regm 268 or reg, reg, t1 269}; 270 271def macroop BTS_M_R { 272 limm t1, imm 273 srai t2, t1, "(env.dataSize == 8) ? 3 : ((env.dataSize == 4) ? 2 : 1)" 274 add t2, t2, base 275 limm t3, 1 276 rol t3, t3, reg 277 ldst t1, seg, [scale, index, t2], disp 278 sext t0, t1, reg, flags=(CF,) 279 or t1, t1, t3 280 st t1, seg, [scale, index, t2], disp 281}; 282 283def macroop BTS_P_R { 284 rdip t7 285 limm t1, imm 286 srai t2, t1, "(env.dataSize == 8) ? 3 : ((env.dataSize == 4) ? 2 : 1)" 287 limm t3, 1 288 rol t3, t3, reg 289 ldst t1, seg, [1, t2, t7] 290 sext t0, t1, reg, flags=(CF,) 291 or t1, t1, t3 292 st t1, seg, [scale, index, t2], disp 293}; 294''' |