1# Copyright (c) 2008 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 111 unchanged lines hidden (view full) --- 120 ori t4, reg, 0x2 121 mov reg, reg, t4, flags=(nCEZF,) 122 mov t1, t1, t3, flags=(nCEZF,) 123 124 # Bit 1 125 srli t3, t1, 1, dataSize=8, flags=(EZF,) 126 ori t4, reg, 0x1 127 mov reg, reg, t4, flags=(nCEZF,) |
128 129end: 130 fault "NoFault" 131}; 132 133def macroop BSR_R_M { 134 135 movi t1, t1, t0, dataSize=8 --- 35 unchanged lines hidden (view full) --- 171 ori t4, reg, 0x2 172 mov reg, reg, t4, flags=(nCEZF,) 173 mov t1, t1, t3, flags=(nCEZF,) 174 175 # Bit 1 176 srli t3, t1, 1, dataSize=8, flags=(EZF,) 177 ori t4, reg, 0x1 178 mov reg, reg, t4, flags=(nCEZF,) |
179 180end: 181 fault "NoFault" 182}; 183 184def macroop BSR_R_P { 185 186 rdip t7 --- 36 unchanged lines hidden (view full) --- 223 ori t4, reg, 0x2 224 mov reg, reg, t4, flags=(nCEZF,) 225 mov t1, t1, t3, flags=(nCEZF,) 226 227 # Bit 1 228 srli t3, t1, 1, dataSize=8, flags=(EZF,) 229 ori t4, reg, 0x1 230 mov reg, reg, t4, flags=(nCEZF,) |
231 232end: 233 fault "NoFault" 234}; 235 236def macroop BSF_R_R { 237 # Determine if the input was zero, and also move it to a temp reg. 238 mov t1, t1, t0, dataSize=8 239 and t1, regm, regm, flags=(ZF,) 240 bri t0, label("end"), flags=(CZF,) 241 242 # Zero out the result register 243 movi reg, reg, 0 244 245 subi t2, t1, 1 246 xor t1, t2, t1 247 |
248 |
249 # Bit 6 |
250 srli t3, t1, 32, dataSize=8, flags=(EZF,) 251 ori t4, reg, 32 252 mov reg, reg, t4, flags=(nCEZF,) |
253 mov t1, t1, t3, flags=(nCEZF,) 254 255 # Bit 5 |
256 srli t3, t1, 16, dataSize=8, flags=(EZF,) 257 ori t4, reg, 16 258 mov reg, reg, t4, flags=(nCEZF,) |
259 mov t1, t1, t3, flags=(nCEZF,) 260 261 # Bit 4 |
262 srli t3, t1, 8, dataSize=8, flags=(EZF,) 263 ori t4, reg, 8 264 mov reg, reg, t4, flags=(nCEZF,) |
265 mov t1, t1, t3, flags=(nCEZF,) 266 267 # Bit 3 |
268 srli t3, t1, 4, dataSize=8, flags=(EZF,) 269 ori t4, reg, 4 270 mov reg, reg, t4, flags=(nCEZF,) |
271 mov t1, t1, t3, flags=(nCEZF,) 272 273 # Bit 2 |
274 srli t3, t1, 2, dataSize=8, flags=(EZF,) 275 ori t4, reg, 2 276 mov reg, reg, t4, flags=(nCEZF,) |
277 mov t1, t1, t3, flags=(nCEZF,) 278 279 # Bit 1 |
280 srli t3, t1, 1, dataSize=8, flags=(EZF,) 281 ori t4, reg, 1 282 mov reg, reg, t4, flags=(nCEZF,) |
283 284end: 285 fault "NoFault" 286}; 287 288def macroop BSF_R_M { 289 290 mov t1, t1, t0, dataSize=8 --- 5 unchanged lines hidden (view full) --- 296 297 # Zero out the result register 298 mov reg, reg, t0 299 300 subi t2, t1, 1 301 xor t1, t2, t1 302 303 # Bit 6 |
304 srli t3, t1, 32, dataSize=8, flags=(EZF,) 305 ori t4, reg, 32 306 mov reg, reg, t4, flags=(nCEZF,) |
307 mov t1, t1, t3, flags=(nCEZF,) 308 309 # Bit 5 |
310 srli t3, t1, 16, dataSize=8, flags=(EZF,) 311 ori t4, reg, 16 312 mov reg, reg, t4, flags=(nCEZF,) |
313 mov t1, t1, t3, flags=(nCEZF,) 314 315 # Bit 4 |
316 srli t3, t1, 8, dataSize=8, flags=(EZF,) 317 ori t4, reg, 8 318 mov reg, reg, t4, flags=(nCEZF,) |
319 mov t1, t1, t3, flags=(nCEZF,) 320 321 # Bit 3 |
322 srli t3, t1, 4, dataSize=8, flags=(EZF,) 323 ori t4, reg, 4 324 mov reg, reg, t4, flags=(nCEZF,) |
325 mov t1, t1, t3, flags=(nCEZF,) 326 327 # Bit 2 |
328 srli t3, t1, 2, dataSize=8, flags=(EZF,) 329 ori t4, reg, 2 330 mov reg, reg, t4, flags=(nCEZF,) |
331 mov t1, t1, t3, flags=(nCEZF,) 332 333 # Bit 1 |
334 srli t3, t1, 1, dataSize=8, flags=(EZF,) 335 ori t4, reg, 1 336 mov reg, reg, t4, flags=(nCEZF,) |
337 mov t1, t1, t3, flags=(nCEZF,) 338 339end: 340 fault "NoFault" 341}; 342 343def macroop BSF_R_P { 344 --- 7 unchanged lines hidden (view full) --- 352 353 # Zero out the result register 354 mov reg, reg, t0 355 356 subi t2, t1, 1 357 xor t1, t2, t1 358 359 # Bit 6 |
360 srli t3, t1, 32, dataSize=8, flags=(EZF,) 361 ori t4, reg, 32 362 mov reg, reg, t4, flags=(nCEZF,) |
363 mov t1, t1, t3, flags=(nCEZF,) 364 365 # Bit 5 |
366 srli t3, t1, 16, dataSize=8, flags=(EZF,) 367 ori t4, reg, 16 368 mov reg, reg, t4, flags=(nCEZF,) |
369 mov t1, t1, t3, flags=(nCEZF,) 370 371 # Bit 4 |
372 srli t3, t1, 8, dataSize=8, flags=(EZF,) 373 ori t4, reg, 8 374 mov reg, reg, t4, flags=(nCEZF,) |
375 mov t1, t1, t3, flags=(nCEZF,) 376 377 # Bit 3 |
378 srli t3, t1, 4, dataSize=8, flags=(EZF,) 379 ori t4, reg, 4 380 mov reg, reg, t4, flags=(nCEZF,) |
381 mov t1, t1, t3, flags=(nCEZF,) 382 383 # Bit 2 |
384 srli t3, t1, 2, dataSize=8, flags=(EZF,) 385 ori t4, reg, 2 386 mov reg, reg, t4, flags=(nCEZF,) |
387 mov t1, t1, t3, flags=(nCEZF,) 388 389 # Bit 1 |
390 srli t3, t1, 1, dataSize=8, flags=(EZF,) 391 ori t4, reg, 1 392 mov reg, reg, t4, flags=(nCEZF,) |
393 mov t1, t1, t3, flags=(nCEZF,) 394 395end: 396 fault "NoFault" 397}; 398''' |