bit_scan.py (5414:bed5152f6368) | bit_scan.py (5415:5c28e3dbdc8e) |
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1# Copyright (c) 2008 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 236 unchanged lines hidden (view full) --- 245 # Zero out the result register 246 movi reg, reg, 0 247 248 subi t2, t1, 1 249 xor t1, t2, t1 250 251 # Bit 6 252 srli t3, t1, 32, dataSize=8 | 1# Copyright (c) 2008 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 236 unchanged lines hidden (view full) --- 245 # Zero out the result register 246 movi reg, reg, 0 247 248 subi t2, t1, 1 249 xor t1, t2, t1 250 251 # Bit 6 252 srli t3, t1, 32, dataSize=8 |
253 andi t3, t3, 32 254 or reg, reg, t3 | 253 andi t4, t3, 32, flags=(EZF,) 254 or reg, reg, t4 255 mov t1, t1, t3, flags=(nCEZF,) |
255 256 # Bit 5 257 srli t3, t1, 16, dataSize=8 | 256 257 # Bit 5 258 srli t3, t1, 16, dataSize=8 |
258 andi t3, t3, 16 259 or reg, reg, t3 | 259 andi t4, t3, 16, flags=(EZF,) 260 or reg, reg, t4 261 mov t1, t1, t3, flags=(nCEZF,) |
260 261 # Bit 4 262 srli t3, t1, 8, dataSize=8 | 262 263 # Bit 4 264 srli t3, t1, 8, dataSize=8 |
263 andi t3, t3, 8 264 or reg, reg, t3 | 265 andi t4, t3, 8, flags=(EZF,) 266 or reg, reg, t4 267 mov t1, t1, t3, flags=(nCEZF,) |
265 266 # Bit 3 267 srli t3, t1, 4, dataSize=8 | 268 269 # Bit 3 270 srli t3, t1, 4, dataSize=8 |
268 andi t3, t3, 4 269 or reg, reg, t3 | 271 andi t4, t3, 4, flags=(EZF,) 272 or reg, reg, t4 273 mov t1, t1, t3, flags=(nCEZF,) |
270 271 # Bit 2 272 srli t3, t1, 2, dataSize=8 | 274 275 # Bit 2 276 srli t3, t1, 2, dataSize=8 |
273 andi t3, t3, 2 274 or reg, reg, t3 | 277 andi t4, t3, 2, flags=(EZF,) 278 or reg, reg, t4 279 mov t1, t1, t3, flags=(nCEZF,) |
275 276 # Bit 1 277 srli t3, t1, 1, dataSize=8 | 280 281 # Bit 1 282 srli t3, t1, 1, dataSize=8 |
278 andi t3, t3, 1 279 or reg, reg, t3 | 283 andi t4, t3, 1, flags=(EZF,) 284 or reg, reg, t4 285 mov t1, t1, t3, flags=(nCEZF,) |
280 281end: 282 fault "NoFault" 283}; 284 285def macroop BSF_R_M { 286 287 mov t1, t1, t0, dataSize=8 --- 6 unchanged lines hidden (view full) --- 294 # Zero out the result register 295 mov reg, reg, t0 296 297 subi t2, t1, 1 298 xor t1, t2, t1 299 300 # Bit 6 301 srli t3, t1, 32, dataSize=8 | 286 287end: 288 fault "NoFault" 289}; 290 291def macroop BSF_R_M { 292 293 mov t1, t1, t0, dataSize=8 --- 6 unchanged lines hidden (view full) --- 300 # Zero out the result register 301 mov reg, reg, t0 302 303 subi t2, t1, 1 304 xor t1, t2, t1 305 306 # Bit 6 307 srli t3, t1, 32, dataSize=8 |
302 andi t3, t3, 32 303 or reg, reg, t3 | 308 andi t4, t3, 32, flags=(EZF,) 309 or reg, reg, t4 310 mov t1, t1, t3, flags=(nCEZF,) |
304 305 # Bit 5 306 srli t3, t1, 16, dataSize=8 | 311 312 # Bit 5 313 srli t3, t1, 16, dataSize=8 |
307 andi t3, t3, 16 308 or reg, reg, t3 | 314 andi t4, t3, 16, flags=(EZF,) 315 or reg, reg, t4 316 mov t1, t1, t3, flags=(nCEZF,) |
309 310 # Bit 4 311 srli t3, t1, 8, dataSize=8 | 317 318 # Bit 4 319 srli t3, t1, 8, dataSize=8 |
312 andi t3, t3, 8 313 or reg, reg, t3 | 320 andi t4, t3, 8, flags=(EZF,) 321 or reg, reg, t4 322 mov t1, t1, t3, flags=(nCEZF,) |
314 315 # Bit 3 316 srli t3, t1, 4, dataSize=8 | 323 324 # Bit 3 325 srli t3, t1, 4, dataSize=8 |
317 andi t3, t3, 4 318 or reg, reg, t3 | 326 andi t4, t3, 4, flags=(EZF,) 327 or reg, reg, t4 328 mov t1, t1, t3, flags=(nCEZF,) |
319 320 # Bit 2 321 srli t3, t1, 2, dataSize=8 | 329 330 # Bit 2 331 srli t3, t1, 2, dataSize=8 |
322 andi t3, t3, 2 323 or reg, reg, t3 | 332 andi t4, t3, 2, flags=(EZF,) 333 or reg, reg, t4 334 mov t1, t1, t3, flags=(nCEZF,) |
324 325 # Bit 1 326 srli t3, t1, 1, dataSize=8 | 335 336 # Bit 1 337 srli t3, t1, 1, dataSize=8 |
327 andi t3, t3, 1 328 or reg, reg, t3 | 338 andi t4, t3, 1, flags=(EZF,) 339 or reg, reg, t4 340 mov t1, t1, t3, flags=(nCEZF,) |
329 330end: 331 fault "NoFault" 332}; 333 334def macroop BSF_R_P { 335 336 rdip t7 --- 7 unchanged lines hidden (view full) --- 344 # Zero out the result register 345 mov reg, reg, t0 346 347 subi t2, t1, 1 348 xor t1, t2, t1 349 350 # Bit 6 351 srli t3, t1, 32, dataSize=8 | 341 342end: 343 fault "NoFault" 344}; 345 346def macroop BSF_R_P { 347 348 rdip t7 --- 7 unchanged lines hidden (view full) --- 356 # Zero out the result register 357 mov reg, reg, t0 358 359 subi t2, t1, 1 360 xor t1, t2, t1 361 362 # Bit 6 363 srli t3, t1, 32, dataSize=8 |
352 andi t3, t3, 32 353 or reg, reg, t3 | 364 andi t4, t3, 32, flags=(EZF,) 365 or reg, reg, t4 366 mov t1, t1, t3, flags=(nCEZF,) |
354 355 # Bit 5 356 srli t3, t1, 16, dataSize=8 | 367 368 # Bit 5 369 srli t3, t1, 16, dataSize=8 |
357 andi t3, t3, 16 358 or reg, reg, t3 | 370 andi t4, t3, 16, flags=(EZF,) 371 or reg, reg, t4 372 mov t1, t1, t3, flags=(nCEZF,) |
359 360 # Bit 4 361 srli t3, t1, 8, dataSize=8 | 373 374 # Bit 4 375 srli t3, t1, 8, dataSize=8 |
362 andi t3, t3, 8 363 or reg, reg, t3 | 376 andi t4, t3, 8, flags=(EZF,) 377 or reg, reg, t4 378 mov t1, t1, t3, flags=(nCEZF,) |
364 365 # Bit 3 366 srli t3, t1, 4, dataSize=8 | 379 380 # Bit 3 381 srli t3, t1, 4, dataSize=8 |
367 andi t3, t3, 4 368 or reg, reg, t3 | 382 andi t4, t3, 4, flags=(EZF,) 383 or reg, reg, t4 384 mov t1, t1, t3, flags=(nCEZF,) |
369 370 # Bit 2 371 srli t3, t1, 2, dataSize=8 | 385 386 # Bit 2 387 srli t3, t1, 2, dataSize=8 |
372 andi t3, t3, 2 373 or reg, reg, t3 | 388 andi t4, t3, 2, flags=(EZF,) 389 or reg, reg, t4 390 mov t1, t1, t3, flags=(nCEZF,) |
374 375 # Bit 1 376 srli t3, t1, 1, dataSize=8 | 391 392 # Bit 1 393 srli t3, t1, 1, dataSize=8 |
377 andi t3, t3, 1 378 or reg, reg, t3 | 394 andi t4, t3, 1, flags=(EZF,) 395 or reg, reg, t4 396 mov t1, t1, t3, flags=(nCEZF,) |
379 380end: 381 fault "NoFault" 382}; 383''' | 397 398end: 399 fault "NoFault" 400}; 401''' |