bit_scan.py (5332:0e25e0b6982c) | bit_scan.py (5333:0e394c08dcbc) |
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1# Copyright (c) 2008 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 70 unchanged lines hidden (view full) --- 79# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 80# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 81# 82# Authors: Gabe Black 83 84microcode = ''' 85def macroop BSF_R_R { 86 # Determine if the input was zero, and also move it to a temp reg. | 1# Copyright (c) 2008 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 70 unchanged lines hidden (view full) --- 79# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 80# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 81# 82# Authors: Gabe Black 83 84microcode = ''' 85def macroop BSF_R_R { 86 # Determine if the input was zero, and also move it to a temp reg. |
87 movi t1, t1, t0, dataSize=8 |
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87 and t1, regm, regm, flags=(ZF,) 88 bri t0, label("end"), flags=(CZF,) 89 90 # Zero out the result register 91 movi reg, reg, 0x0 92 93 # Bit 6 | 88 and t1, regm, regm, flags=(ZF,) 89 bri t0, label("end"), flags=(CZF,) 90 91 # Zero out the result register 92 movi reg, reg, 0x0 93 94 # Bit 6 |
94 limm t2, 0xFFFFFFFF00000000 95 and t3, t2, t1, flags=(EZF,) | 95 srli t3, t1, 32, dataSize=8, flags=(EZF,) |
96 ori t4, reg, 0x20 97 mov reg, reg, t4, flags=(nCEZF,) 98 mov t1, t1, t3, flags=(nCEZF,) 99 100 # Bit 5 | 96 ori t4, reg, 0x20 97 mov reg, reg, t4, flags=(nCEZF,) 98 mov t1, t1, t3, flags=(nCEZF,) 99 100 # Bit 5 |
101 limm t2, 0xFFFF0000FFFF0000 102 and t3, t2, t1, flags=(EZF,) | 101 srli t3, t1, 16, dataSize=8, flags=(EZF,) |
103 ori t4, reg, 0x10 104 mov reg, reg, t4, flags=(nCEZF,) 105 mov t1, t1, t3, flags=(nCEZF,) 106 107 # Bit 4 | 102 ori t4, reg, 0x10 103 mov reg, reg, t4, flags=(nCEZF,) 104 mov t1, t1, t3, flags=(nCEZF,) 105 106 # Bit 4 |
108 limm t2, 0xFF00FF00FF00FF00 109 and t3, t2, t1, flags=(EZF,) | 107 srli t3, t1, 8, dataSize=8, flags=(EZF,) |
110 ori t4, reg, 0x8 111 mov reg, reg, t4, flags=(nCEZF,) 112 mov t1, t1, t3, flags=(nCEZF,) 113 114 # Bit 3 | 108 ori t4, reg, 0x8 109 mov reg, reg, t4, flags=(nCEZF,) 110 mov t1, t1, t3, flags=(nCEZF,) 111 112 # Bit 3 |
115 limm t2, 0xF0F0F0F0F0F0F0F0 116 and t3, t2, t1, flags=(EZF,) | 113 srli t3, t1, 4, dataSize=8, flags=(EZF,) |
117 ori t4, reg, 0x4 118 mov reg, reg, t4, flags=(nCEZF,) 119 mov t1, t1, t3, flags=(nCEZF,) 120 121 # Bit 2 | 114 ori t4, reg, 0x4 115 mov reg, reg, t4, flags=(nCEZF,) 116 mov t1, t1, t3, flags=(nCEZF,) 117 118 # Bit 2 |
122 limm t2, 0xCCCCCCCCCCCCCCCC 123 and t3, t2, t1, flags=(EZF,) | 119 srli t3, t1, 2, dataSize=8, flags=(EZF,) |
124 ori t4, reg, 0x2 125 mov reg, reg, t4, flags=(nCEZF,) 126 mov t1, t1, t3, flags=(nCEZF,) 127 128 # Bit 1 | 120 ori t4, reg, 0x2 121 mov reg, reg, t4, flags=(nCEZF,) 122 mov t1, t1, t3, flags=(nCEZF,) 123 124 # Bit 1 |
129 limm t2, 0xAAAAAAAAAAAAAAAA 130 and t3, t2, t1, flags=(EZF,) | 125 srli t3, t1, 1, dataSize=8, flags=(EZF,) |
131 ori t4, reg, 0x1 132 mov reg, reg, t4, flags=(nCEZF,) 133 mov t1, t1, t3, flags=(nCEZF,) 134 135end: 136 fault "NoFault" 137}; 138 139def macroop BSF_R_M { 140 | 126 ori t4, reg, 0x1 127 mov reg, reg, t4, flags=(nCEZF,) 128 mov t1, t1, t3, flags=(nCEZF,) 129 130end: 131 fault "NoFault" 132}; 133 134def macroop BSF_R_M { 135 |
136 movi t1, t1, t0, dataSize=8 |
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141 ld t1, seg, sib, disp 142 143 # Determine if the input was zero, and also move it to a temp reg. 144 and t1, t1, t1, flags=(ZF,) 145 bri t0, label("end"), flags=(CZF,) 146 147 # Zero out the result register 148 movi reg, reg, 0x0 149 150 # Bit 6 | 137 ld t1, seg, sib, disp 138 139 # Determine if the input was zero, and also move it to a temp reg. 140 and t1, t1, t1, flags=(ZF,) 141 bri t0, label("end"), flags=(CZF,) 142 143 # Zero out the result register 144 movi reg, reg, 0x0 145 146 # Bit 6 |
151 limm t2, 0xFFFFFFFF00000000 152 and t3, t2, t1, flags=(EZF,) | 147 srli t3, t1, 32, dataSize=8, flags=(EZF,) |
153 ori t4, reg, 0x20 154 mov reg, reg, t4, flags=(nCEZF,) 155 mov t1, t1, t3, flags=(nCEZF,) 156 157 # Bit 5 | 148 ori t4, reg, 0x20 149 mov reg, reg, t4, flags=(nCEZF,) 150 mov t1, t1, t3, flags=(nCEZF,) 151 152 # Bit 5 |
158 limm t2, 0xFFFF0000FFFF0000 159 and t3, t2, t1, flags=(EZF,) | 153 srli t3, t1, 16, dataSize=8, flags=(EZF,) |
160 ori t4, reg, 0x10 161 mov reg, reg, t4, flags=(nCEZF,) 162 mov t1, t1, t3, flags=(nCEZF,) 163 164 # Bit 4 | 154 ori t4, reg, 0x10 155 mov reg, reg, t4, flags=(nCEZF,) 156 mov t1, t1, t3, flags=(nCEZF,) 157 158 # Bit 4 |
165 limm t2, 0xFF00FF00FF00FF00 166 and t3, t2, t1, flags=(EZF,) | 159 srli t3, t1, 8, dataSize=8, flags=(EZF,) |
167 ori t4, reg, 0x8 168 mov reg, reg, t4, flags=(nCEZF,) 169 mov t1, t1, t3, flags=(nCEZF,) 170 171 # Bit 3 | 160 ori t4, reg, 0x8 161 mov reg, reg, t4, flags=(nCEZF,) 162 mov t1, t1, t3, flags=(nCEZF,) 163 164 # Bit 3 |
172 limm t2, 0xF0F0F0F0F0F0F0F0 173 and t3, t2, t1, flags=(EZF,) | 165 srli t3, t1, 4, dataSize=8, flags=(EZF,) |
174 ori t4, reg, 0x4 175 mov reg, reg, t4, flags=(nCEZF,) 176 mov t1, t1, t3, flags=(nCEZF,) 177 178 # Bit 2 | 166 ori t4, reg, 0x4 167 mov reg, reg, t4, flags=(nCEZF,) 168 mov t1, t1, t3, flags=(nCEZF,) 169 170 # Bit 2 |
179 limm t2, 0xCCCCCCCCCCCCCCCC 180 and t3, t2, t1, flags=(EZF,) | 171 srli t3, t1, 2, dataSize=8, flags=(EZF,) |
181 ori t4, reg, 0x2 182 mov reg, reg, t4, flags=(nCEZF,) 183 mov t1, t1, t3, flags=(nCEZF,) 184 185 # Bit 1 | 172 ori t4, reg, 0x2 173 mov reg, reg, t4, flags=(nCEZF,) 174 mov t1, t1, t3, flags=(nCEZF,) 175 176 # Bit 1 |
186 limm t2, 0xAAAAAAAAAAAAAAAA 187 and t3, t2, t1, flags=(EZF,) | 177 srli t3, t1, 1, dataSize=8, flags=(EZF,) |
188 ori t4, reg, 0x1 189 mov reg, reg, t4, flags=(nCEZF,) 190 mov t1, t1, t3, flags=(nCEZF,) 191 192end: 193 fault "NoFault" 194}; 195 196def macroop BSF_R_P { 197 198 rdip t7 | 178 ori t4, reg, 0x1 179 mov reg, reg, t4, flags=(nCEZF,) 180 mov t1, t1, t3, flags=(nCEZF,) 181 182end: 183 fault "NoFault" 184}; 185 186def macroop BSF_R_P { 187 188 rdip t7 |
189 movi t1, t1, t0, dataSize=8 |
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199 ld t1, seg, riprel, disp 200 201 # Determine if the input was zero, and also move it to a temp reg. 202 and t1, t1, t1, flags=(ZF,) 203 bri t0, label("end"), flags=(CZF,) 204 205 # Zero out the result register 206 movi reg, reg, 0x0 207 208 # Bit 6 | 190 ld t1, seg, riprel, disp 191 192 # Determine if the input was zero, and also move it to a temp reg. 193 and t1, t1, t1, flags=(ZF,) 194 bri t0, label("end"), flags=(CZF,) 195 196 # Zero out the result register 197 movi reg, reg, 0x0 198 199 # Bit 6 |
209 limm t2, 0xFFFFFFFF00000000 210 and t3, t2, t1, flags=(EZF,) | 200 srli t3, t1, 32, dataSize=8, flags=(EZF,) |
211 ori t4, reg, 0x20 212 mov reg, reg, t4, flags=(nCEZF,) 213 mov t1, t1, t3, flags=(nCEZF,) 214 215 # Bit 5 | 201 ori t4, reg, 0x20 202 mov reg, reg, t4, flags=(nCEZF,) 203 mov t1, t1, t3, flags=(nCEZF,) 204 205 # Bit 5 |
216 limm t2, 0xFFFF0000FFFF0000 217 and t3, t2, t1, flags=(EZF,) | 206 srli t3, t1, 16, dataSize=8, flags=(EZF,) |
218 ori t4, reg, 0x10 219 mov reg, reg, t4, flags=(nCEZF,) 220 mov t1, t1, t3, flags=(nCEZF,) 221 222 # Bit 4 | 207 ori t4, reg, 0x10 208 mov reg, reg, t4, flags=(nCEZF,) 209 mov t1, t1, t3, flags=(nCEZF,) 210 211 # Bit 4 |
223 limm t2, 0xFF00FF00FF00FF00 224 and t3, t2, t1, flags=(EZF,) | 212 srli t3, t1, 8, dataSize=8, flags=(EZF,) |
225 ori t4, reg, 0x8 226 mov reg, reg, t4, flags=(nCEZF,) 227 mov t1, t1, t3, flags=(nCEZF,) 228 229 # Bit 3 | 213 ori t4, reg, 0x8 214 mov reg, reg, t4, flags=(nCEZF,) 215 mov t1, t1, t3, flags=(nCEZF,) 216 217 # Bit 3 |
230 limm t2, 0xF0F0F0F0F0F0F0F0 231 and t3, t2, t1, flags=(EZF,) | 218 srli t3, t1, 4, dataSize=8, flags=(EZF,) |
232 ori t4, reg, 0x4 233 mov reg, reg, t4, flags=(nCEZF,) 234 mov t1, t1, t3, flags=(nCEZF,) 235 236 # Bit 2 | 219 ori t4, reg, 0x4 220 mov reg, reg, t4, flags=(nCEZF,) 221 mov t1, t1, t3, flags=(nCEZF,) 222 223 # Bit 2 |
237 limm t2, 0xCCCCCCCCCCCCCCCC 238 and t3, t2, t1, flags=(EZF,) | 224 srli t3, t1, 2, dataSize=8, flags=(EZF,) |
239 ori t4, reg, 0x2 240 mov reg, reg, t4, flags=(nCEZF,) 241 mov t1, t1, t3, flags=(nCEZF,) 242 243 # Bit 1 | 225 ori t4, reg, 0x2 226 mov reg, reg, t4, flags=(nCEZF,) 227 mov t1, t1, t3, flags=(nCEZF,) 228 229 # Bit 1 |
244 limm t2, 0xAAAAAAAAAAAAAAAA 245 and t3, t2, t1, flags=(EZF,) | 230 srli t3, t1, 1, dataSize=8, flags=(EZF,) |
246 ori t4, reg, 0x1 247 mov reg, reg, t4, flags=(nCEZF,) 248 mov t1, t1, t3, flags=(nCEZF,) 249 250end: 251 fault "NoFault" 252}; 253 254def macroop BSR_R_R { 255 # Determine if the input was zero, and also move it to a temp reg. | 231 ori t4, reg, 0x1 232 mov reg, reg, t4, flags=(nCEZF,) 233 mov t1, t1, t3, flags=(nCEZF,) 234 235end: 236 fault "NoFault" 237}; 238 239def macroop BSR_R_R { 240 # Determine if the input was zero, and also move it to a temp reg. |
241 mov t1, t1, t0, dataSize=8 |
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256 and t1, regm, regm, flags=(ZF,) 257 bri t0, label("end"), flags=(CZF,) 258 259 # Zero out the result register 260 movi reg, reg, 0 261 | 242 and t1, regm, regm, flags=(ZF,) 243 bri t0, label("end"), flags=(CZF,) 244 245 # Zero out the result register 246 movi reg, reg, 0 247 |
248 subi t2, t1, 1 249 xor t1, t2, t1 250 |
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262 # Bit 6 | 251 # Bit 6 |
263 limm t2, 0x00000000FFFFFFFF 264 and t3, t2, t1, flags=(EZF,) 265 ori t4, reg, 0x20 266 mov reg, reg, t4, flags=(CEZF,) 267 mov t1, t1, t3, flags=(nCEZF,) | 252 srli t3, t1, 32, dataSize=8 253 andi t3, t3, 32 254 or reg, reg, t3 |
268 269 # Bit 5 | 255 256 # Bit 5 |
270 limm t2, 0x0000FFFF0000FFFF 271 and t3, t2, t1, flags=(EZF,) 272 ori t4, reg, 0x10 273 mov reg, reg, t4, flags=(CEZF,) 274 mov t1, t1, t3, flags=(nCEZF,) | 257 srli t3, t1, 16, dataSize=8 258 andi t3, t3, 16 259 or reg, reg, t3 |
275 276 # Bit 4 | 260 261 # Bit 4 |
277 limm t2, 0x00FF00FF00FF00FF 278 and t3, t2, t1, flags=(EZF,) 279 ori t4, reg, 0x8 280 mov reg, reg, t4, flags=(CEZF,) 281 mov t1, t1, t3, flags=(nCEZF,) | 262 srli t3, t1, 8, dataSize=8 263 andi t3, t3, 8 264 or reg, reg, t3 |
282 283 # Bit 3 | 265 266 # Bit 3 |
284 limm t2, 0x0F0F0F0F0F0F0F0F 285 and t3, t2, t1, flags=(EZF,) 286 ori t4, reg, 0x4 287 mov reg, reg, t4, flags=(CEZF,) 288 mov t1, t1, t3, flags=(nCEZF,) | 267 srli t3, t1, 4, dataSize=8 268 andi t3, t3, 4 269 or reg, reg, t3 |
289 290 # Bit 2 | 270 271 # Bit 2 |
291 limm t2, 0x3333333333333333 292 and t3, t2, t1, flags=(EZF,) 293 ori t4, reg, 0x2 294 mov reg, reg, t4, flags=(CEZF,) 295 mov t1, t1, t3, flags=(nCEZF,) | 272 srli t3, t1, 2, dataSize=8 273 andi t3, t3, 2 274 or reg, reg, t3 |
296 297 # Bit 1 | 275 276 # Bit 1 |
298 limm t2, 0x5555555555555555 299 and t3, t2, t1, flags=(EZF,) 300 ori t4, reg, 0x1 301 mov reg, reg, t4, flags=(CEZF,) 302 mov t1, t1, t3, flags=(nCEZF,) | 277 srli t3, t1, 1, dataSize=8 278 andi t3, t3, 1 279 or reg, reg, t3 |
303 304end: 305 fault "NoFault" 306}; 307 308def macroop BSR_R_M { 309 | 280 281end: 282 fault "NoFault" 283}; 284 285def macroop BSR_R_M { 286 |
287 mov t1, t1, t0, dataSize=8 |
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310 ld t1, seg, sib, disp 311 312 # Determine if the input was zero, and also move it to a temp reg. 313 and t1, t1, t1, flags=(ZF,) 314 bri t0, label("end"), flags=(CZF,) 315 316 # Zero out the result register 317 mov reg, reg, t0 318 | 288 ld t1, seg, sib, disp 289 290 # Determine if the input was zero, and also move it to a temp reg. 291 and t1, t1, t1, flags=(ZF,) 292 bri t0, label("end"), flags=(CZF,) 293 294 # Zero out the result register 295 mov reg, reg, t0 296 |
297 subi t2, t1, 1 298 xor t1, t2, t1 299 |
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319 # Bit 6 | 300 # Bit 6 |
320 limm t2, 0x00000000FFFFFFFF 321 and t3, t2, t1, flags=(EZF,) 322 ori t4, reg, 0x20 323 mov reg, reg, t4, flags=(CEZF,) 324 mov t1, t1, t3, flags=(nCEZF,) | 301 srli t3, t1, 32, dataSize=8 302 andi t3, t3, 32 303 or reg, reg, t3 |
325 326 # Bit 5 | 304 305 # Bit 5 |
327 limm t2, 0x0000FFFF0000FFFF 328 and t3, t2, t1, flags=(EZF,) 329 ori t4, reg, 0x10 330 mov reg, reg, t4, flags=(CEZF,) 331 mov t1, t1, t3, flags=(nCEZF,) | 306 srli t3, t1, 16, dataSize=8 307 andi t3, t3, 16 308 or reg, reg, t3 |
332 333 # Bit 4 | 309 310 # Bit 4 |
334 limm t2, 0x00FF00FF00FF00FF 335 and t3, t2, t1, flags=(EZF,) 336 ori t4, reg, 0x8 337 mov reg, reg, t4, flags=(CEZF,) 338 mov t1, t1, t3, flags=(nCEZF,) | 311 srli t3, t1, 8, dataSize=8 312 andi t3, t3, 8 313 or reg, reg, t3 |
339 340 # Bit 3 | 314 315 # Bit 3 |
341 limm t2, 0x0F0F0F0F0F0F0F0F 342 and t3, t2, t1, flags=(EZF,) 343 ori t4, reg, 0x4 344 mov reg, reg, t4, flags=(CEZF,) 345 mov t1, t1, t3, flags=(nCEZF,) | 316 srli t3, t1, 4, dataSize=8 317 andi t3, t3, 4 318 or reg, reg, t3 |
346 347 # Bit 2 | 319 320 # Bit 2 |
348 limm t2, 0x3333333333333333 349 and t3, t2, t1, flags=(EZF,) 350 ori t4, reg, 0x2 351 mov reg, reg, t4, flags=(CEZF,) 352 mov t1, t1, t3, flags=(nCEZF,) | 321 srli t3, t1, 2, dataSize=8 322 andi t3, t3, 2 323 or reg, reg, t3 |
353 354 # Bit 1 | 324 325 # Bit 1 |
355 limm t2, 0x5555555555555555 356 and t3, t2, t1, flags=(EZF,) 357 ori t4, reg, 0x1 358 mov reg, reg, t4, flags=(CEZF,) 359 mov t1, t1, t3, flags=(nCEZF,) | 326 srli t3, t1, 1, dataSize=8 327 andi t3, t3, 1 328 or reg, reg, t3 |
360 361end: 362 fault "NoFault" 363}; 364 365def macroop BSR_R_P { 366 367 rdip t7 | 329 330end: 331 fault "NoFault" 332}; 333 334def macroop BSR_R_P { 335 336 rdip t7 |
337 mov t1, t1, t0, dataSize=8 |
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368 ld t1, seg, riprel, disp 369 370 # Determine if the input was zero, and also move it to a temp reg. 371 and t1, t1, t1, flags=(ZF,) 372 bri t0, label("end"), flags=(CZF,) 373 374 # Zero out the result register 375 mov reg, reg, t0 376 | 338 ld t1, seg, riprel, disp 339 340 # Determine if the input was zero, and also move it to a temp reg. 341 and t1, t1, t1, flags=(ZF,) 342 bri t0, label("end"), flags=(CZF,) 343 344 # Zero out the result register 345 mov reg, reg, t0 346 |
347 subi t2, t1, 1 348 xor t1, t2, t1 349 |
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377 # Bit 6 | 350 # Bit 6 |
378 limm t2, 0x00000000FFFFFFFF 379 and t3, t2, t1, flags=(EZF,) 380 ori t4, reg, 0x20 381 mov reg, reg, t4, flags=(CEZF,) 382 mov t1, t1, t3, flags=(nCEZF,) | 351 srli t3, t1, 32, dataSize=8 352 andi t3, t3, 32 353 or reg, reg, t3 |
383 384 # Bit 5 | 354 355 # Bit 5 |
385 limm t2, 0x0000FFFF0000FFFF 386 and t3, t2, t1, flags=(EZF,) 387 ori t4, reg, 0x10 388 mov reg, reg, t4, flags=(CEZF,) 389 mov t1, t1, t3, flags=(nCEZF,) | 356 srli t3, t1, 16, dataSize=8 357 andi t3, t3, 16 358 or reg, reg, t3 |
390 391 # Bit 4 | 359 360 # Bit 4 |
392 limm t2, 0x00FF00FF00FF00FF 393 and t3, t2, t1, flags=(EZF,) 394 ori t4, reg, 0x8 395 mov reg, reg, t4, flags=(CEZF,) 396 mov t1, t1, t3, flags=(nCEZF,) | 361 srli t3, t1, 8, dataSize=8 362 andi t3, t3, 8 363 or reg, reg, t3 |
397 398 # Bit 3 | 364 365 # Bit 3 |
399 limm t2, 0x0F0F0F0F0F0F0F0F 400 and t3, t2, t1, flags=(EZF,) 401 ori t4, reg, 0x4 402 mov reg, reg, t4, flags=(CEZF,) 403 mov t1, t1, t3, flags=(nCEZF,) | 366 srli t3, t1, 4, dataSize=8 367 andi t3, t3, 4 368 or reg, reg, t3 |
404 405 # Bit 2 | 369 370 # Bit 2 |
406 limm t2, 0x3333333333333333 407 and t3, t2, t1, flags=(EZF,) 408 ori t4, reg, 0x2 409 mov reg, reg, t4, flags=(CEZF,) 410 mov t1, t1, t3, flags=(nCEZF,) | 371 srli t3, t1, 2, dataSize=8 372 andi t3, t3, 2 373 or reg, reg, t3 |
411 412 # Bit 1 | 374 375 # Bit 1 |
413 limm t2, 0x5555555555555555 414 and t3, t2, t1, flags=(EZF,) 415 ori t4, reg, 0x1 416 mov reg, reg, t4, flags=(CEZF,) 417 mov t1, t1, t3, flags=(nCEZF,) | 376 srli t3, t1, 1, dataSize=8 377 andi t3, t3, 1 378 or reg, reg, t3 |
418 419end: 420 fault "NoFault" 421}; 422''' | 379 380end: 381 fault "NoFault" 382}; 383''' |