cache_and_memory_management.py (5543:3af77710f397) | cache_and_memory_management.py (5920:5a9c976270d6) |
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1# Copyright (c) 2007 The Hewlett-Packard Development Company 2# All rights reserved. 3# 4# Redistribution and use of this software in source and binary forms, 5# with or without modification, are permitted provided that the 6# following conditions are met: 7# 8# The software must be used only for Non-Commercial Use which means any --- 39 unchanged lines hidden (view full) --- 48# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 49# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 50# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 51# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 52# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 53# 54# Authors: Gabe Black 55 | 1# Copyright (c) 2007 The Hewlett-Packard Development Company 2# All rights reserved. 3# 4# Redistribution and use of this software in source and binary forms, 5# with or without modification, are permitted provided that the 6# following conditions are met: 7# 8# The software must be used only for Non-Commercial Use which means any --- 39 unchanged lines hidden (view full) --- 48# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 49# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 50# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 51# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 52# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 53# 54# Authors: Gabe Black 55 |
56microcode = "" | 56microcode = ''' 57def macroop PREFETCH_M 58{ 59 ld t0, seg, sib, disp, dataSize=1, prefetch=True 60}; 61 62def macroop PREFETCH_P 63{ 64 rdip t7 65 ld t0, seg, riprel, disp, dataSize=1, prefetch=True 66}; 67 68def macroop PREFETCH_T0_M 69{ 70 ld t0, seg, sib, disp, dataSize=1, prefetch=True 71}; 72 73def macroop PREFETCH_T0_P 74{ 75 rdip t7 76 ld t0, seg, riprel, disp, dataSize=1, prefetch=True 77}; 78 79''' 80 |
57#let {{ 58# class LFENCE(Inst): 59# "GenFault ${new UnimpInstFault}" 60# class SFENCE(Inst): 61# "GenFault ${new UnimpInstFault}" 62# class MFENCE(Inst): 63# "GenFault ${new UnimpInstFault}" 64# class PREFETCHlevel(Inst): 65# "GenFault ${new UnimpInstFault}" | 81#let {{ 82# class LFENCE(Inst): 83# "GenFault ${new UnimpInstFault}" 84# class SFENCE(Inst): 85# "GenFault ${new UnimpInstFault}" 86# class MFENCE(Inst): 87# "GenFault ${new UnimpInstFault}" 88# class PREFETCHlevel(Inst): 89# "GenFault ${new UnimpInstFault}" |
66# class PREFETCH(Inst): 67# "GenFault ${new UnimpInstFault}" | |
68# class PREFETCHW(Inst): 69# "GenFault ${new UnimpInstFault}" 70# class CLFLUSH(Inst): 71# "GenFault ${new UnimpInstFault}" 72#}}; | 90# class PREFETCHW(Inst): 91# "GenFault ${new UnimpInstFault}" 92# class CLFLUSH(Inst): 93# "GenFault ${new UnimpInstFault}" 94#}}; |