two_byte_opcodes.isa (5238:95f494fd38bd) | two_byte_opcodes.isa (5240:6dc723c9c6a9) |
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1// Copyright (c) 2007 The Hewlett-Packard Development Company 2// All rights reserved. 3// 4// Redistribution and use of this software in source and binary forms, 5// with or without modification, are permitted provided that the 6// following conditions are met: 7// 8// The software must be used only for Non-Commercial Use which means any --- 643 unchanged lines hidden (view full) --- 652 0x6: SETLE(Eb); 653 0x7: SETNLE(Eb); 654 } 655 } 656 0x14: decode OPCODE_OP_BOTTOM3 { 657 0x0: push_fs(); 658 0x1: pop_fs(); 659 0x2: Inst::CPUID(rAd); | 1// Copyright (c) 2007 The Hewlett-Packard Development Company 2// All rights reserved. 3// 4// Redistribution and use of this software in source and binary forms, 5// with or without modification, are permitted provided that the 6// following conditions are met: 7// 8// The software must be used only for Non-Commercial Use which means any --- 643 unchanged lines hidden (view full) --- 652 0x6: SETLE(Eb); 653 0x7: SETNLE(Eb); 654 } 655 } 656 0x14: decode OPCODE_OP_BOTTOM3 { 657 0x0: push_fs(); 658 0x1: pop_fs(); 659 0x2: Inst::CPUID(rAd); |
660 0x3: bt_Ev_Gv(); | 660 0x3: Inst::BT(Ev,Gv); |
661 0x4: shld_Ev_Gv_Ib(); 662 0x5: shld_Ev_Gv_rCl(); 663 0x6: xbts_and_cmpxchg(); 664 0x7: ibts_and_cmpxchg(); 665 } 666 0x15: decode OPCODE_OP_BOTTOM3 { 667 0x0: push_gs(); 668 0x1: pop_gs(); 669 0x2: rsm_smm(); | 661 0x4: shld_Ev_Gv_Ib(); 662 0x5: shld_Ev_Gv_rCl(); 663 0x6: xbts_and_cmpxchg(); 664 0x7: ibts_and_cmpxchg(); 665 } 666 0x15: decode OPCODE_OP_BOTTOM3 { 667 0x0: push_gs(); 668 0x1: pop_gs(); 669 0x2: rsm_smm(); |
670 0x3: bts_Ev_Gv(); | 670 0x3: Inst::BTS(Ev,Gv); |
671 0x4: shrd_Ev_Gv_Ib(); 672 0x5: shrd_Ev_Gv_rCl(); 673 //0x6: group16(); 674 0x6: decode MODRM_MOD { 675 0x3: decode MODRM_REG { 676 0x5: lfence(); 677 0x6: mfence(); 678 0x7: sfence(); --- 7 unchanged lines hidden (view full) --- 686 } 687 } 688 0x7: Inst::IMUL(Gv,Ev); 689 } 690 0x16: decode OPCODE_OP_BOTTOM3 { 691 0x0: Inst::CMPXCHG(Eb,Gb); 692 0x1: Inst::CMPXCHG(Ev,Gv); 693 0x2: lss_Gz_Mp(); | 671 0x4: shrd_Ev_Gv_Ib(); 672 0x5: shrd_Ev_Gv_rCl(); 673 //0x6: group16(); 674 0x6: decode MODRM_MOD { 675 0x3: decode MODRM_REG { 676 0x5: lfence(); 677 0x6: mfence(); 678 0x7: sfence(); --- 7 unchanged lines hidden (view full) --- 686 } 687 } 688 0x7: Inst::IMUL(Gv,Ev); 689 } 690 0x16: decode OPCODE_OP_BOTTOM3 { 691 0x0: Inst::CMPXCHG(Eb,Gb); 692 0x1: Inst::CMPXCHG(Ev,Gv); 693 0x2: lss_Gz_Mp(); |
694 0x3: btr_Ev_Gv(); | 694 0x3: Inst::BTR(Ev,Gv); |
695 0x4: lfs_Gz_Mp(); 696 0x5: lgs_Gz_Mp(); 697 //The size of the second operand in these instructions should 698 //really be "b" or "w", but it's set to v in order to have a 699 //consistent register size. This shouldn't affect behavior. 700 0x6: Inst::MOVZX_B(Gv,Ev); 701 0x7: Inst::MOVZX_W(Gv,Ev); 702 } 703 0x17: decode OPCODE_OP_BOTTOM3 { 704 0x0: jmpe_Jz(); // IA-64? | 695 0x4: lfs_Gz_Mp(); 696 0x5: lgs_Gz_Mp(); 697 //The size of the second operand in these instructions should 698 //really be "b" or "w", but it's set to v in order to have a 699 //consistent register size. This shouldn't affect behavior. 700 0x6: Inst::MOVZX_B(Gv,Ev); 701 0x7: Inst::MOVZX_W(Gv,Ev); 702 } 703 0x17: decode OPCODE_OP_BOTTOM3 { 704 0x0: jmpe_Jz(); // IA-64? |
705 //0x1: group11_UD2(); 706 0x1: Inst::UD2(); 707 //0x2: group8_Ev_Ib(); 708 0x2: decode MODRM_REG { 709 0x4: bt_Ev_Ib(); 710 0x5: bts_Ev_Ib(); 711 0x6: btr_Ev_Ib(); 712 0x7: btc_Ev_Ib(); 713 default: Inst::UD2(); | 705 format Inst { 706 //0x1: group11_UD2(); 707 0x1: UD2(); 708 //0x2: group8_Ev_Ib(); 709 0x2: decode MODRM_REG { 710 0x4: BT(Ev,Ib); 711 0x5: BTS(Ev,Ib); 712 0x6: BTR(Ev,Ib); 713 0x7: BTC(Ev,Ib); 714 default: UD2(); 715 } 716 0x3: BTC(Ev,Gv); |
714 } | 717 } |
715 0x3: btc_Ev_Gv(); | |
716 0x4: bsf_Gv_Ev(); 717 0x5: bsr_Gv_Ev(); 718 //The size of the second operand in these instructions should 719 //really be "b" or "w", but it's set to v in order to have a 720 //consistent register size. This shouldn't affect behavior. 721 0x6: Inst::MOVSX_B(Gv,Ev); 722 0x7: Inst::MOVSX_W(Gv,Ev); 723 } --- 231 unchanged lines hidden --- | 718 0x4: bsf_Gv_Ev(); 719 0x5: bsr_Gv_Ev(); 720 //The size of the second operand in these instructions should 721 //really be "b" or "w", but it's set to v in order to have a 722 //consistent register size. This shouldn't affect behavior. 723 0x6: Inst::MOVSX_B(Gv,Ev); 724 0x7: Inst::MOVSX_W(Gv,Ev); 725 } --- 231 unchanged lines hidden --- |