isa.hh (10934:5af8f40d8f2c) | isa.hh (10935:acd48ddd725f) |
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1/* 2 * Copyright (c) 2009 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 78 unchanged lines hidden (view full) --- 87 88 int 89 flattenCCIndex(int reg) const 90 { 91 return reg; 92 } 93 94 int | 1/* 2 * Copyright (c) 2009 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 78 unchanged lines hidden (view full) --- 87 88 int 89 flattenCCIndex(int reg) const 90 { 91 return reg; 92 } 93 94 int |
95 flattenVectorIndex(int reg) const 96 { 97 return reg; 98 } 99 100 int | |
101 flattenMiscIndex(int reg) const 102 { 103 return reg; 104 } 105 106 void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; 107 void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; 108 109 void startup(ThreadContext *tc); 110 111 /// Explicitly import the otherwise hidden startup 112 using SimObject::startup; 113 114 }; 115} 116 117#endif | 95 flattenMiscIndex(int reg) const 96 { 97 return reg; 98 } 99 100 void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; 101 void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; 102 103 void startup(ThreadContext *tc); 104 105 /// Explicitly import the otherwise hidden startup 106 using SimObject::startup; 107 108 }; 109} 110 111#endif |