isa.hh (10033:21c14a2b2117) isa.hh (10035:2a0fbecfeb14)
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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65
66 MiscReg readMiscRegNoEffect(int miscReg);
67 MiscReg readMiscReg(int miscReg, ThreadContext *tc);
68
69 void setMiscRegNoEffect(int miscReg, MiscReg val);
70 void setMiscReg(int miscReg, MiscReg val, ThreadContext *tc);
71
72 int
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 56 unchanged lines hidden (view full) ---

65
66 MiscReg readMiscRegNoEffect(int miscReg);
67 MiscReg readMiscReg(int miscReg, ThreadContext *tc);
68
69 void setMiscRegNoEffect(int miscReg, MiscReg val);
70 void setMiscReg(int miscReg, MiscReg val, ThreadContext *tc);
71
72 int
73 flattenIntIndex(int reg)
73 flattenIntIndex(int reg) const
74 {
75 return reg & ~IntFoldBit;
76 }
77
78 int
74 {
75 return reg & ~IntFoldBit;
76 }
77
78 int
79 flattenFloatIndex(int reg)
79 flattenFloatIndex(int reg) const
80 {
81 if (reg >= NUM_FLOATREGS) {
82 reg = FLOATREG_STACK(reg - NUM_FLOATREGS,
83 regVal[MISCREG_X87_TOP]);
84 }
85 return reg;
86 }
87
88 int
80 {
81 if (reg >= NUM_FLOATREGS) {
82 reg = FLOATREG_STACK(reg - NUM_FLOATREGS,
83 regVal[MISCREG_X87_TOP]);
84 }
85 return reg;
86 }
87
88 int
89 flattenCCIndex(int reg)
89 flattenCCIndex(int reg) const
90 {
91 return reg;
92 }
93
94 int
90 {
91 return reg;
92 }
93
94 int
95 flattenMiscIndex(int reg)
95 flattenMiscIndex(int reg) const
96 {
97 return reg;
98 }
99
100 void serialize(std::ostream &os);
101 void unserialize(Checkpoint *cp, const std::string &section);
102 void startup(ThreadContext *tc);
103
104 /// Explicitly import the otherwise hidden startup
105 using SimObject::startup;
106
107 };
108}
109
110#endif
96 {
97 return reg;
98 }
99
100 void serialize(std::ostream &os);
101 void unserialize(Checkpoint *cp, const std::string &section);
102 void startup(ThreadContext *tc);
103
104 /// Explicitly import the otherwise hidden startup
105 using SimObject::startup;
106
107 };
108}
109
110#endif