1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#ifndef __ARCH_X86_ISA_HH__
32#define __ARCH_X86_ISA_HH__
33
34#include <iostream>
35#include <string>
36
37#include "arch/x86/regs/float.hh"
38#include "arch/x86/regs/misc.hh"
39#include "arch/x86/registers.hh"
40#include "base/types.hh"
| 1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#ifndef __ARCH_X86_ISA_HH__
32#define __ARCH_X86_ISA_HH__
33
34#include <iostream>
35#include <string>
36
37#include "arch/x86/regs/float.hh"
38#include "arch/x86/regs/misc.hh"
39#include "arch/x86/registers.hh"
40#include "base/types.hh"
|
| 41#include "sim/sim_object.hh"
|
41
42class Checkpoint;
43class EventManager;
44class ThreadContext;
| 42
43class Checkpoint;
44class EventManager;
45class ThreadContext;
|
| 46struct X86ISAParams;
|
45
46namespace X86ISA
47{
| 47
48namespace X86ISA
49{
|
48 class ISA
| 50 class ISA : public SimObject
|
49 {
50 protected:
51 MiscReg regVal[NUM_MISCREGS];
52 void updateHandyM5Reg(Efer efer, CR0 cr0,
53 SegAttr csAttr, SegAttr ssAttr, RFLAGS rflags,
54 ThreadContext *tc);
55
56 public:
| 51 {
52 protected:
53 MiscReg regVal[NUM_MISCREGS];
54 void updateHandyM5Reg(Efer efer, CR0 cr0,
55 SegAttr csAttr, SegAttr ssAttr, RFLAGS rflags,
56 ThreadContext *tc);
57
58 public:
|
| 59 typedef X86ISAParams Params;
60
|
57 void clear();
58
| 61 void clear();
62
|
59 ISA()
60 {
61 clear();
62 }
| 63 ISA(Params *p);
64 const Params *params() const;
|
63
64 MiscReg readMiscRegNoEffect(int miscReg);
65 MiscReg readMiscReg(int miscReg, ThreadContext *tc);
66
67 void setMiscRegNoEffect(int miscReg, MiscReg val);
68 void setMiscReg(int miscReg, MiscReg val, ThreadContext *tc);
69
70 int
71 flattenIntIndex(int reg)
72 {
73 return reg & ~IntFoldBit;
74 }
75
76 int
77 flattenFloatIndex(int reg)
78 {
79 if (reg >= NUM_FLOATREGS) {
80 reg = FLOATREG_STACK(reg - NUM_FLOATREGS,
81 regVal[MISCREG_X87_TOP]);
82 }
83 return reg;
84 }
85
86 void serialize(EventManager *em, std::ostream &os);
87 void unserialize(EventManager *em, Checkpoint *cp,
88 const std::string §ion);
89 };
90}
91
92#endif
| 65
66 MiscReg readMiscRegNoEffect(int miscReg);
67 MiscReg readMiscReg(int miscReg, ThreadContext *tc);
68
69 void setMiscRegNoEffect(int miscReg, MiscReg val);
70 void setMiscReg(int miscReg, MiscReg val, ThreadContext *tc);
71
72 int
73 flattenIntIndex(int reg)
74 {
75 return reg & ~IntFoldBit;
76 }
77
78 int
79 flattenFloatIndex(int reg)
80 {
81 if (reg >= NUM_FLOATREGS) {
82 reg = FLOATREG_STACK(reg - NUM_FLOATREGS,
83 regVal[MISCREG_X87_TOP]);
84 }
85 return reg;
86 }
87
88 void serialize(EventManager *em, std::ostream &os);
89 void unserialize(EventManager *em, Checkpoint *cp,
90 const std::string §ion);
91 };
92}
93
94#endif
|