isa.cc (9372:7ba317c33683) isa.cc (9376:270c9a75e91f)
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 14 unchanged lines hidden (view full) ---

23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#include "arch/x86/decoder.hh"
31#include "arch/x86/isa.hh"
32#include "arch/x86/tlb.hh"
33#include "cpu/base.hh"
34#include "cpu/thread_context.hh"
35#include "sim/serialize.hh"
36
37namespace X86ISA
38{
39
40void
41ISA::updateHandyM5Reg(Efer efer, CR0 cr0,
32#include "arch/x86/isa.hh"
33#include "arch/x86/tlb.hh"
34#include "cpu/base.hh"
35#include "cpu/thread_context.hh"
36#include "sim/serialize.hh"
37
38namespace X86ISA
39{
40
41void
42ISA::updateHandyM5Reg(Efer efer, CR0 cr0,
42 SegAttr csAttr, SegAttr ssAttr, RFLAGS rflags)
43 SegAttr csAttr, SegAttr ssAttr, RFLAGS rflags,
44 ThreadContext *tc)
43{
44 HandyM5Reg m5reg = 0;
45 if (efer.lma) {
46 m5reg.mode = LongMode;
47 if (csAttr.longMode)
48 m5reg.submode = SixtyFourBitMode;
49 else
50 m5reg.submode = CompatabilityMode;

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89 m5reg.stack = 3;
90 } else if (ssAttr.defaultSize) {
91 m5reg.stack = 2;
92 } else {
93 m5reg.stack = 1;
94 }
95
96 regVal[MISCREG_M5_REG] = m5reg;
45{
46 HandyM5Reg m5reg = 0;
47 if (efer.lma) {
48 m5reg.mode = LongMode;
49 if (csAttr.longMode)
50 m5reg.submode = SixtyFourBitMode;
51 else
52 m5reg.submode = CompatabilityMode;

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91 m5reg.stack = 3;
92 } else if (ssAttr.defaultSize) {
93 m5reg.stack = 2;
94 } else {
95 m5reg.stack = 1;
96 }
97
98 regVal[MISCREG_M5_REG] = m5reg;
99 if (tc)
100 tc->getDecoderPtr()->setM5Reg(m5reg);
97}
98
99void
100ISA::clear()
101{
102 // Blank everything. 0 might not be an appropriate value for some things,
103 // but it is for most.
104 memset(regVal, 0, NumMiscRegs * sizeof(MiscReg));

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179 }
180 //This must always be 1.
181 newCR0.et = 1;
182 newVal = newCR0;
183 updateHandyM5Reg(regVal[MISCREG_EFER],
184 newCR0,
185 regVal[MISCREG_CS_ATTR],
186 regVal[MISCREG_SS_ATTR],
101}
102
103void
104ISA::clear()
105{
106 // Blank everything. 0 might not be an appropriate value for some things,
107 // but it is for most.
108 memset(regVal, 0, NumMiscRegs * sizeof(MiscReg));

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183 }
184 //This must always be 1.
185 newCR0.et = 1;
186 newVal = newCR0;
187 updateHandyM5Reg(regVal[MISCREG_EFER],
188 newCR0,
189 regVal[MISCREG_CS_ATTR],
190 regVal[MISCREG_SS_ATTR],
187 regVal[MISCREG_RFLAGS]);
191 regVal[MISCREG_RFLAGS],
192 tc);
188 }
189 break;
190 case MISCREG_CR2:
191 break;
192 case MISCREG_CR3:
193 tc->getITBPtr()->invalidateNonGlobal();
194 tc->getDTBPtr()->invalidateNonGlobal();
195 break;

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220 regVal[MISCREG_SS_EFF_BASE] = regVal[MISCREG_SS_BASE];
221 regVal[MISCREG_DS_EFF_BASE] = regVal[MISCREG_DS_BASE];
222 }
223 }
224 updateHandyM5Reg(regVal[MISCREG_EFER],
225 regVal[MISCREG_CR0],
226 newCSAttr,
227 regVal[MISCREG_SS_ATTR],
193 }
194 break;
195 case MISCREG_CR2:
196 break;
197 case MISCREG_CR3:
198 tc->getITBPtr()->invalidateNonGlobal();
199 tc->getDTBPtr()->invalidateNonGlobal();
200 break;

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225 regVal[MISCREG_SS_EFF_BASE] = regVal[MISCREG_SS_BASE];
226 regVal[MISCREG_DS_EFF_BASE] = regVal[MISCREG_DS_BASE];
227 }
228 }
229 updateHandyM5Reg(regVal[MISCREG_EFER],
230 regVal[MISCREG_CR0],
231 newCSAttr,
232 regVal[MISCREG_SS_ATTR],
228 regVal[MISCREG_RFLAGS]);
233 regVal[MISCREG_RFLAGS],
234 tc);
229 }
230 break;
231 case MISCREG_SS_ATTR:
232 updateHandyM5Reg(regVal[MISCREG_EFER],
233 regVal[MISCREG_CR0],
234 regVal[MISCREG_CS_ATTR],
235 val,
235 }
236 break;
237 case MISCREG_SS_ATTR:
238 updateHandyM5Reg(regVal[MISCREG_EFER],
239 regVal[MISCREG_CR0],
240 regVal[MISCREG_CS_ATTR],
241 val,
236 regVal[MISCREG_RFLAGS]);
242 regVal[MISCREG_RFLAGS],
243 tc);
237 break;
238 // These segments always actually use their bases, or in other words
239 // their effective bases must stay equal to their actual bases.
240 case MISCREG_FS_BASE:
241 case MISCREG_GS_BASE:
242 case MISCREG_HS_BASE:
243 case MISCREG_TSL_BASE:
244 case MISCREG_TSG_BASE:

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335 case MISCREG_M5_REG:
336 // Writing anything to the m5reg with side effects makes it update
337 // based on the current values of the relevant registers. The actual
338 // value written is discarded.
339 updateHandyM5Reg(regVal[MISCREG_EFER],
340 regVal[MISCREG_CR0],
341 regVal[MISCREG_CS_ATTR],
342 regVal[MISCREG_SS_ATTR],
244 break;
245 // These segments always actually use their bases, or in other words
246 // their effective bases must stay equal to their actual bases.
247 case MISCREG_FS_BASE:
248 case MISCREG_GS_BASE:
249 case MISCREG_HS_BASE:
250 case MISCREG_TSL_BASE:
251 case MISCREG_TSG_BASE:

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342 case MISCREG_M5_REG:
343 // Writing anything to the m5reg with side effects makes it update
344 // based on the current values of the relevant registers. The actual
345 // value written is discarded.
346 updateHandyM5Reg(regVal[MISCREG_EFER],
347 regVal[MISCREG_CR0],
348 regVal[MISCREG_CS_ATTR],
349 regVal[MISCREG_SS_ATTR],
343 regVal[MISCREG_RFLAGS]);
350 regVal[MISCREG_RFLAGS],
351 tc);
344 return;
345 default:
346 break;
347 }
348 setMiscRegNoEffect(miscReg, newVal);
349}
350
351void

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358ISA::unserialize(EventManager *em, Checkpoint * cp,
359 const std::string & section)
360{
361 UNSERIALIZE_ARRAY(regVal, NumMiscRegs);
362 updateHandyM5Reg(regVal[MISCREG_EFER],
363 regVal[MISCREG_CR0],
364 regVal[MISCREG_CS_ATTR],
365 regVal[MISCREG_SS_ATTR],
352 return;
353 default:
354 break;
355 }
356 setMiscRegNoEffect(miscReg, newVal);
357}
358
359void

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366ISA::unserialize(EventManager *em, Checkpoint * cp,
367 const std::string & section)
368{
369 UNSERIALIZE_ARRAY(regVal, NumMiscRegs);
370 updateHandyM5Reg(regVal[MISCREG_EFER],
371 regVal[MISCREG_CR0],
372 regVal[MISCREG_CS_ATTR],
373 regVal[MISCREG_SS_ATTR],
366 regVal[MISCREG_RFLAGS]);
374 regVal[MISCREG_RFLAGS],
375 NULL);
367}
368
369}
376}
377
378}