isa.cc (6313:95f69a436c82) isa.cc (6336:25635830e33c)
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 14 unchanged lines hidden (view full) ---

23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 14 unchanged lines hidden (view full) ---

23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#include "arch/x86/isa.hh"
32#include "arch/x86/floatregs.hh"
31#include "arch/x86/floatregs.hh"
32#include "arch/x86/isa.hh"
33#include "arch/x86/tlb.hh"
34#include "cpu/base.hh"
33#include "cpu/thread_context.hh"
35#include "cpu/thread_context.hh"
36#include "sim/serialize.hh"
34
35namespace X86ISA
36{
37
38void
37
38namespace X86ISA
39{
40
41void
42ISA::updateHandyM5Reg(Efer efer, CR0 cr0,
43 SegAttr csAttr, SegAttr ssAttr, RFLAGS rflags)
44{
45 HandyM5Reg m5reg;
46 if (efer.lma) {
47 m5reg.mode = LongMode;
48 if (csAttr.longMode)
49 m5reg.submode = SixtyFourBitMode;
50 else
51 m5reg.submode = CompatabilityMode;
52 } else {
53 m5reg.mode = LegacyMode;
54 if (cr0.pe) {
55 if (rflags.vm)
56 m5reg.submode = Virtual8086Mode;
57 else
58 m5reg.submode = ProtectedMode;
59 } else {
60 m5reg.submode = RealMode;
61 }
62 }
63 m5reg.cpl = csAttr.dpl;
64 m5reg.paging = cr0.pg;
65 m5reg.prot = cr0.pe;
66
67 // Compute the default and alternate operand size.
68 if (m5reg.submode == SixtyFourBitMode || csAttr.defaultSize) {
69 m5reg.defOp = 2;
70 m5reg.altOp = 1;
71 } else {
72 m5reg.defOp = 1;
73 m5reg.altOp = 2;
74 }
75
76 // Compute the default and alternate address size.
77 if (m5reg.submode == SixtyFourBitMode) {
78 m5reg.defAddr = 3;
79 m5reg.altAddr = 2;
80 } else if (csAttr.defaultSize) {
81 m5reg.defAddr = 2;
82 m5reg.altAddr = 1;
83 } else {
84 m5reg.defAddr = 1;
85 m5reg.altAddr = 2;
86 }
87
88 // Compute the stack size
89 if (m5reg.submode == SixtyFourBitMode) {
90 m5reg.stack = 3;
91 } else if (ssAttr.defaultSize) {
92 m5reg.stack = 2;
93 } else {
94 m5reg.stack = 1;
95 }
96
97 regVal[MISCREG_M5_REG] = m5reg;
98}
99
100void
39ISA::clear()
40{
101ISA::clear()
102{
41 miscRegFile.clear();
103 // Blank everything. 0 might not be an appropriate value for some things,
104 // but it is for most.
105 memset(regVal, 0, NumMiscRegs * sizeof(MiscReg));
106 regVal[MISCREG_DR6] = (mask(8) << 4) | (mask(16) << 16);
107 regVal[MISCREG_DR7] = 1 << 10;
42}
43
44MiscReg
45ISA::readMiscRegNoEffect(int miscReg)
46{
108}
109
110MiscReg
111ISA::readMiscRegNoEffect(int miscReg)
112{
47 return miscRegFile.readRegNoEffect((MiscRegIndex)miscReg);
113 // Make sure we're not dealing with an illegal control register.
114 // Instructions should filter out these indexes, and nothing else should
115 // attempt to read them directly.
116 assert( miscReg != MISCREG_CR1 &&
117 !(miscReg > MISCREG_CR4 &&
118 miscReg < MISCREG_CR8) &&
119 !(miscReg > MISCREG_CR8 &&
120 miscReg <= MISCREG_CR15));
121
122 return regVal[miscReg];
48}
49
50MiscReg
123}
124
125MiscReg
51ISA::readMiscReg(int miscReg, ThreadContext *tc)
126ISA::readMiscReg(int miscReg, ThreadContext * tc)
52{
127{
53 return miscRegFile.readReg((MiscRegIndex)miscReg, tc);
128 if (miscReg == MISCREG_TSC) {
129 return regVal[MISCREG_TSC] + tc->getCpuPtr()->curCycle();
130 }
131 return readMiscRegNoEffect(miscReg);
54}
55
56void
132}
133
134void
57ISA::setMiscRegNoEffect(int miscReg, const MiscReg val)
135ISA::setMiscRegNoEffect(int miscReg, MiscReg val)
58{
136{
59 miscRegFile.setRegNoEffect((MiscRegIndex)miscReg, val);
137 // Make sure we're not dealing with an illegal control register.
138 // Instructions should filter out these indexes, and nothing else should
139 // attempt to write to them directly.
140 assert( miscReg != MISCREG_CR1 &&
141 !(miscReg > MISCREG_CR4 &&
142 miscReg < MISCREG_CR8) &&
143 !(miscReg > MISCREG_CR8 &&
144 miscReg <= MISCREG_CR15));
145 regVal[miscReg] = val;
60}
61
62void
146}
147
148void
63ISA::setMiscReg(int miscReg, const MiscReg val, ThreadContext *tc)
149ISA::setMiscReg(int miscReg, MiscReg val, ThreadContext * tc)
64{
150{
65 miscRegFile.setReg((MiscRegIndex)miscReg, val, tc);
151 MiscReg newVal = val;
152 switch(miscReg)
153 {
154 case MISCREG_CR0:
155 {
156 CR0 toggled = regVal[miscReg] ^ val;
157 CR0 newCR0 = val;
158 Efer efer = regVal[MISCREG_EFER];
159 if (toggled.pg && efer.lme) {
160 if (newCR0.pg) {
161 //Turning on long mode
162 efer.lma = 1;
163 regVal[MISCREG_EFER] = efer;
164 } else {
165 //Turning off long mode
166 efer.lma = 0;
167 regVal[MISCREG_EFER] = efer;
168 }
169 }
170 if (toggled.pg) {
171 tc->getITBPtr()->invalidateAll();
172 tc->getDTBPtr()->invalidateAll();
173 }
174 //This must always be 1.
175 newCR0.et = 1;
176 newVal = newCR0;
177 updateHandyM5Reg(regVal[MISCREG_EFER],
178 newCR0,
179 regVal[MISCREG_CS_ATTR],
180 regVal[MISCREG_SS_ATTR],
181 regVal[MISCREG_RFLAGS]);
182 }
183 break;
184 case MISCREG_CR2:
185 break;
186 case MISCREG_CR3:
187 tc->getITBPtr()->invalidateNonGlobal();
188 tc->getDTBPtr()->invalidateNonGlobal();
189 break;
190 case MISCREG_CR4:
191 {
192 CR4 toggled = regVal[miscReg] ^ val;
193 if (toggled.pae || toggled.pse || toggled.pge) {
194 tc->getITBPtr()->invalidateAll();
195 tc->getDTBPtr()->invalidateAll();
196 }
197 }
198 break;
199 case MISCREG_CR8:
200 break;
201 case MISCREG_CS_ATTR:
202 {
203 SegAttr toggled = regVal[miscReg] ^ val;
204 SegAttr newCSAttr = val;
205 if (toggled.longMode) {
206 if (newCSAttr.longMode) {
207 regVal[MISCREG_ES_EFF_BASE] = 0;
208 regVal[MISCREG_CS_EFF_BASE] = 0;
209 regVal[MISCREG_SS_EFF_BASE] = 0;
210 regVal[MISCREG_DS_EFF_BASE] = 0;
211 } else {
212 regVal[MISCREG_ES_EFF_BASE] = regVal[MISCREG_ES_BASE];
213 regVal[MISCREG_CS_EFF_BASE] = regVal[MISCREG_CS_BASE];
214 regVal[MISCREG_SS_EFF_BASE] = regVal[MISCREG_SS_BASE];
215 regVal[MISCREG_DS_EFF_BASE] = regVal[MISCREG_DS_BASE];
216 }
217 }
218 updateHandyM5Reg(regVal[MISCREG_EFER],
219 regVal[MISCREG_CR0],
220 newCSAttr,
221 regVal[MISCREG_SS_ATTR],
222 regVal[MISCREG_RFLAGS]);
223 }
224 break;
225 case MISCREG_SS_ATTR:
226 updateHandyM5Reg(regVal[MISCREG_EFER],
227 regVal[MISCREG_CR0],
228 regVal[MISCREG_CS_ATTR],
229 val,
230 regVal[MISCREG_RFLAGS]);
231 break;
232 // These segments always actually use their bases, or in other words
233 // their effective bases must stay equal to their actual bases.
234 case MISCREG_FS_BASE:
235 case MISCREG_GS_BASE:
236 case MISCREG_HS_BASE:
237 case MISCREG_TSL_BASE:
238 case MISCREG_TSG_BASE:
239 case MISCREG_TR_BASE:
240 case MISCREG_IDTR_BASE:
241 regVal[MISCREG_SEG_EFF_BASE(miscReg - MISCREG_SEG_BASE_BASE)] = val;
242 break;
243 // These segments ignore their bases in 64 bit mode.
244 // their effective bases must stay equal to their actual bases.
245 case MISCREG_ES_BASE:
246 case MISCREG_CS_BASE:
247 case MISCREG_SS_BASE:
248 case MISCREG_DS_BASE:
249 {
250 Efer efer = regVal[MISCREG_EFER];
251 SegAttr csAttr = regVal[MISCREG_CS_ATTR];
252 if (!efer.lma || !csAttr.longMode) // Check for non 64 bit mode.
253 regVal[MISCREG_SEG_EFF_BASE(miscReg -
254 MISCREG_SEG_BASE_BASE)] = val;
255 }
256 break;
257 case MISCREG_TSC:
258 regVal[MISCREG_TSC] = val - tc->getCpuPtr()->curCycle();
259 return;
260 case MISCREG_DR0:
261 case MISCREG_DR1:
262 case MISCREG_DR2:
263 case MISCREG_DR3:
264 /* These should eventually set up breakpoints. */
265 break;
266 case MISCREG_DR4:
267 miscReg = MISCREG_DR6;
268 /* Fall through to have the same effects as DR6. */
269 case MISCREG_DR6:
270 {
271 DR6 dr6 = regVal[MISCREG_DR6];
272 DR6 newDR6 = val;
273 dr6.b0 = newDR6.b0;
274 dr6.b1 = newDR6.b1;
275 dr6.b2 = newDR6.b2;
276 dr6.b3 = newDR6.b3;
277 dr6.bd = newDR6.bd;
278 dr6.bs = newDR6.bs;
279 dr6.bt = newDR6.bt;
280 newVal = dr6;
281 }
282 break;
283 case MISCREG_DR5:
284 miscReg = MISCREG_DR7;
285 /* Fall through to have the same effects as DR7. */
286 case MISCREG_DR7:
287 {
288 DR7 dr7 = regVal[MISCREG_DR7];
289 DR7 newDR7 = val;
290 dr7.l0 = newDR7.l0;
291 dr7.g0 = newDR7.g0;
292 if (dr7.l0 || dr7.g0) {
293 panic("Debug register breakpoints not implemented.\n");
294 } else {
295 /* Disable breakpoint 0. */
296 }
297 dr7.l1 = newDR7.l1;
298 dr7.g1 = newDR7.g1;
299 if (dr7.l1 || dr7.g1) {
300 panic("Debug register breakpoints not implemented.\n");
301 } else {
302 /* Disable breakpoint 1. */
303 }
304 dr7.l2 = newDR7.l2;
305 dr7.g2 = newDR7.g2;
306 if (dr7.l2 || dr7.g2) {
307 panic("Debug register breakpoints not implemented.\n");
308 } else {
309 /* Disable breakpoint 2. */
310 }
311 dr7.l3 = newDR7.l3;
312 dr7.g3 = newDR7.g3;
313 if (dr7.l3 || dr7.g3) {
314 panic("Debug register breakpoints not implemented.\n");
315 } else {
316 /* Disable breakpoint 3. */
317 }
318 dr7.gd = newDR7.gd;
319 dr7.rw0 = newDR7.rw0;
320 dr7.len0 = newDR7.len0;
321 dr7.rw1 = newDR7.rw1;
322 dr7.len1 = newDR7.len1;
323 dr7.rw2 = newDR7.rw2;
324 dr7.len2 = newDR7.len2;
325 dr7.rw3 = newDR7.rw3;
326 dr7.len3 = newDR7.len3;
327 }
328 break;
329 case MISCREG_M5_REG:
330 // Writing anything to the m5reg with side effects makes it update
331 // based on the current values of the relevant registers. The actual
332 // value written is discarded.
333 updateHandyM5Reg(regVal[MISCREG_EFER],
334 regVal[MISCREG_CR0],
335 regVal[MISCREG_CS_ATTR],
336 regVal[MISCREG_SS_ATTR],
337 regVal[MISCREG_RFLAGS]);
338 return;
339 default:
340 break;
341 }
342 setMiscRegNoEffect(miscReg, newVal);
66}
67
343}
344
345void
346ISA::serialize(EventManager *em, std::ostream & os)
347{
348 SERIALIZE_ARRAY(regVal, NumMiscRegs);
349}
350
351void
352ISA::unserialize(EventManager *em, Checkpoint * cp,
353 const std::string & section)
354{
355 UNSERIALIZE_ARRAY(regVal, NumMiscRegs);
356}
357
68int
69ISA::flattenIntIndex(int reg)
70{
71 //If we need to fold over the index to match byte semantics, do that.
72 //Otherwise, just strip off any extra bits and pass it through.
73 if (reg & (1 << 6))
74 return (reg & (~(1 << 6) - 0x4));
75 else
76 return (reg & ~(1 << 6));
77}
78
79int
80ISA::flattenFloatIndex(int reg)
81{
82 if (reg >= NUM_FLOATREGS) {
358int
359ISA::flattenIntIndex(int reg)
360{
361 //If we need to fold over the index to match byte semantics, do that.
362 //Otherwise, just strip off any extra bits and pass it through.
363 if (reg & (1 << 6))
364 return (reg & (~(1 << 6) - 0x4));
365 else
366 return (reg & ~(1 << 6));
367}
368
369int
370ISA::flattenFloatIndex(int reg)
371{
372 if (reg >= NUM_FLOATREGS) {
83 int top = miscRegFile.readRegNoEffect(MISCREG_X87_TOP);
373 int top = readMiscRegNoEffect(MISCREG_X87_TOP);
84 reg = FLOATREG_STACK(reg - NUM_FLOATREGS, top);
85 }
86 return reg;
87}
88
374 reg = FLOATREG_STACK(reg - NUM_FLOATREGS, top);
375 }
376 return reg;
377}
378
89void
90ISA::serialize(EventManager *em, std::ostream &os)
91{
92 miscRegFile.serialize(os);
93}
379}
94
95void
96ISA::unserialize(EventManager *em, Checkpoint *cp, const std::string &section)
97{
98 miscRegFile.unserialize(cp, section);
99}
100
101}