isa.cc (12692:1eaaa1d75080) isa.cc (13613:a19963be12ca)
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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102 tc->getDecoderPtr()->setM5Reg(m5reg);
103}
104
105void
106ISA::clear()
107{
108 // Blank everything. 0 might not be an appropriate value for some things,
109 // but it is for most.
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 93 unchanged lines hidden (view full) ---

102 tc->getDecoderPtr()->setM5Reg(m5reg);
103}
104
105void
106ISA::clear()
107{
108 // Blank everything. 0 might not be an appropriate value for some things,
109 // but it is for most.
110 memset(regVal, 0, NumMiscRegs * sizeof(MiscReg));
110 memset(regVal, 0, NumMiscRegs * sizeof(RegVal));
111 regVal[MISCREG_DR6] = (mask(8) << 4) | (mask(16) << 16);
112 regVal[MISCREG_DR7] = 1 << 10;
113}
114
115ISA::ISA(Params *p)
116 : SimObject(p)
117{
118 clear();
119}
120
121const X86ISAParams *
122ISA::params() const
123{
124 return dynamic_cast<const Params *>(_params);
125}
126
111 regVal[MISCREG_DR6] = (mask(8) << 4) | (mask(16) << 16);
112 regVal[MISCREG_DR7] = 1 << 10;
113}
114
115ISA::ISA(Params *p)
116 : SimObject(p)
117{
118 clear();
119}
120
121const X86ISAParams *
122ISA::params() const
123{
124 return dynamic_cast<const Params *>(_params);
125}
126
127MiscReg
127RegVal
128ISA::readMiscRegNoEffect(int miscReg) const
129{
130 // Make sure we're not dealing with an illegal control register.
131 // Instructions should filter out these indexes, and nothing else should
132 // attempt to read them directly.
133 assert(isValidMiscReg(miscReg));
134
135 return regVal[miscReg];
136}
137
128ISA::readMiscRegNoEffect(int miscReg) const
129{
130 // Make sure we're not dealing with an illegal control register.
131 // Instructions should filter out these indexes, and nothing else should
132 // attempt to read them directly.
133 assert(isValidMiscReg(miscReg));
134
135 return regVal[miscReg];
136}
137
138MiscReg
138RegVal
139ISA::readMiscReg(int miscReg, ThreadContext * tc)
140{
141 if (miscReg == MISCREG_TSC) {
142 return regVal[MISCREG_TSC] + tc->getCpuPtr()->curCycle();
143 }
144
145 if (miscReg == MISCREG_FSW) {
139ISA::readMiscReg(int miscReg, ThreadContext * tc)
140{
141 if (miscReg == MISCREG_TSC) {
142 return regVal[MISCREG_TSC] + tc->getCpuPtr()->curCycle();
143 }
144
145 if (miscReg == MISCREG_FSW) {
146 MiscReg fsw = regVal[MISCREG_FSW];
147 MiscReg top = regVal[MISCREG_X87_TOP];
146 RegVal fsw = regVal[MISCREG_FSW];
147 RegVal top = regVal[MISCREG_X87_TOP];
148 return insertBits(fsw, 13, 11, top);
149 }
150
151 return readMiscRegNoEffect(miscReg);
152}
153
154void
148 return insertBits(fsw, 13, 11, top);
149 }
150
151 return readMiscRegNoEffect(miscReg);
152}
153
154void
155ISA::setMiscRegNoEffect(int miscReg, MiscReg val)
155ISA::setMiscRegNoEffect(int miscReg, RegVal val)
156{
157 // Make sure we're not dealing with an illegal control register.
158 // Instructions should filter out these indexes, and nothing else should
159 // attempt to write to them directly.
160 assert(isValidMiscReg(miscReg));
161
162 HandyM5Reg m5Reg = regVal[MISCREG_M5_REG];
163 int reg_width = 64;

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189 default:
190 break;
191 }
192
193 regVal[miscReg] = val & mask(reg_width);
194}
195
196void
156{
157 // Make sure we're not dealing with an illegal control register.
158 // Instructions should filter out these indexes, and nothing else should
159 // attempt to write to them directly.
160 assert(isValidMiscReg(miscReg));
161
162 HandyM5Reg m5Reg = regVal[MISCREG_M5_REG];
163 int reg_width = 64;

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189 default:
190 break;
191 }
192
193 regVal[miscReg] = val & mask(reg_width);
194}
195
196void
197ISA::setMiscReg(int miscReg, MiscReg val, ThreadContext * tc)
197ISA::setMiscReg(int miscReg, RegVal val, ThreadContext * tc)
198{
198{
199 MiscReg newVal = val;
199 RegVal newVal = val;
200 switch(miscReg)
201 {
202 case MISCREG_CR0:
203 {
204 CR0 toggled = regVal[miscReg] ^ val;
205 CR0 newCR0 = val;
206 Efer efer = regVal[MISCREG_EFER];
207 if (toggled.pg && efer.lme) {

--- 220 unchanged lines hidden --- 		200 switch(miscReg)
201 {
202 case MISCREG_CR0:
203 {
204 CR0 toggled = regVal[miscReg] ^ val;
205 CR0 newCR0 = val;
206 Efer efer = regVal[MISCREG_EFER];
207 if (toggled.pg && efer.lme) {

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