isa.cc (12368:511bd7aa22d1) isa.cc (12392:e0dbdf30a2a5)
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 302 unchanged lines hidden (view full) ---

311 case MISCREG_DR0:
312 case MISCREG_DR1:
313 case MISCREG_DR2:
314 case MISCREG_DR3:
315 /* These should eventually set up breakpoints. */
316 break;
317 case MISCREG_DR4:
318 miscReg = MISCREG_DR6;
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 302 unchanged lines hidden (view full) ---

311 case MISCREG_DR0:
312 case MISCREG_DR1:
313 case MISCREG_DR2:
314 case MISCREG_DR3:
315 /* These should eventually set up breakpoints. */
316 break;
317 case MISCREG_DR4:
318 miscReg = MISCREG_DR6;
319 /* Fall through to have the same effects as DR6. */
319 M5_FALLTHROUGH;
320 case MISCREG_DR6:
321 {
322 DR6 dr6 = regVal[MISCREG_DR6];
323 DR6 newDR6 = val;
324 dr6.b0 = newDR6.b0;
325 dr6.b1 = newDR6.b1;
326 dr6.b2 = newDR6.b2;
327 dr6.b3 = newDR6.b3;
328 dr6.bd = newDR6.bd;
329 dr6.bs = newDR6.bs;
330 dr6.bt = newDR6.bt;
331 newVal = dr6;
332 }
333 break;
334 case MISCREG_DR5:
335 miscReg = MISCREG_DR7;
320 case MISCREG_DR6:
321 {
322 DR6 dr6 = regVal[MISCREG_DR6];
323 DR6 newDR6 = val;
324 dr6.b0 = newDR6.b0;
325 dr6.b1 = newDR6.b1;
326 dr6.b2 = newDR6.b2;
327 dr6.b3 = newDR6.b3;
328 dr6.bd = newDR6.bd;
329 dr6.bs = newDR6.bs;
330 dr6.bt = newDR6.bt;
331 newVal = dr6;
332 }
333 break;
334 case MISCREG_DR5:
335 miscReg = MISCREG_DR7;
336 /* Fall through to have the same effects as DR7. */
336 M5_FALLTHROUGH;
337 case MISCREG_DR7:
338 {
339 DR7 dr7 = regVal[MISCREG_DR7];
340 DR7 newDR7 = val;
341 dr7.l0 = newDR7.l0;
342 dr7.g0 = newDR7.g0;
343 if (dr7.l0 || dr7.g0) {
344 panic("Debug register breakpoints not implemented.\n");

--- 83 unchanged lines hidden --- 		337 case MISCREG_DR7:
338 {
339 DR7 dr7 = regVal[MISCREG_DR7];
340 DR7 newDR7 = val;
341 dr7.l0 = newDR7.l0;
342 dr7.g0 = newDR7.g0;
343 if (dr7.l0 || dr7.g0) {
344 panic("Debug register breakpoints not implemented.\n");

--- 83 unchanged lines hidden ---