isa.cc (11793:ef606668d247) isa.cc (12368:511bd7aa22d1)
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 131 unchanged lines hidden (view full) ---

140{
141 if (miscReg == MISCREG_TSC) {
142 return regVal[MISCREG_TSC] + tc->getCpuPtr()->curCycle();
143 }
144
145 if (miscReg == MISCREG_FSW) {
146 MiscReg fsw = regVal[MISCREG_FSW];
147 MiscReg top = regVal[MISCREG_X87_TOP];
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 131 unchanged lines hidden (view full) ---

140{
141 if (miscReg == MISCREG_TSC) {
142 return regVal[MISCREG_TSC] + tc->getCpuPtr()->curCycle();
143 }
144
145 if (miscReg == MISCREG_FSW) {
146 MiscReg fsw = regVal[MISCREG_FSW];
147 MiscReg top = regVal[MISCREG_X87_TOP];
148 return (fsw & (~(7ULL << 11))) + (top << 11);
148 return insertBits(fsw, 11, 13, top);
149 }
150
151 return readMiscRegNoEffect(miscReg);
152}
153
154void
155ISA::setMiscRegNoEffect(int miscReg, MiscReg val)
156{
157 // Make sure we're not dealing with an illegal control register.
158 // Instructions should filter out these indexes, and nothing else should
159 // attempt to write to them directly.
160 assert(isValidMiscReg(miscReg));
161
149 }
150
151 return readMiscRegNoEffect(miscReg);
152}
153
154void
155ISA::setMiscRegNoEffect(int miscReg, MiscReg val)
156{
157 // Make sure we're not dealing with an illegal control register.
158 // Instructions should filter out these indexes, and nothing else should
159 // attempt to write to them directly.
160 assert(isValidMiscReg(miscReg));
161
162 HandyM5Reg m5Reg = readMiscRegNoEffect(MISCREG_M5_REG);
162 HandyM5Reg m5Reg = regVal[MISCREG_M5_REG];
163 int reg_width = 64;
163 switch (miscReg) {
164 switch (miscReg) {
164 case MISCREG_FSW:
165 val &= (1ULL << 16) - 1;
166 regVal[miscReg] = val;
167 miscReg = MISCREG_X87_TOP;
168 val <<= 11;
169 case MISCREG_X87_TOP:
165 case MISCREG_X87_TOP:
170 val &= (1ULL << 3) - 1;
166 reg_width = 3;
171 break;
172 case MISCREG_FTW:
167 break;
168 case MISCREG_FTW:
173 val &= (1ULL << 8) - 1;
169 reg_width = 8;
174 break;
170 break;
171 case MISCREG_FSW:
175 case MISCREG_FCW:
176 case MISCREG_FOP:
172 case MISCREG_FCW:
173 case MISCREG_FOP:
177 val &= (1ULL << 16) - 1;
174 reg_width = 16;
178 break;
179 case MISCREG_MXCSR:
175 break;
176 case MISCREG_MXCSR:
180 val &= (1ULL << 32) - 1;
177 reg_width = 32;
181 break;
182 case MISCREG_FISEG:
183 case MISCREG_FOSEG:
184 if (m5Reg.submode != SixtyFourBitMode)
178 break;
179 case MISCREG_FISEG:
180 case MISCREG_FOSEG:
181 if (m5Reg.submode != SixtyFourBitMode)
185 val &= (1ULL << 16) - 1;
182 reg_width = 16;
186 break;
187 case MISCREG_FIOFF:
188 case MISCREG_FOOFF:
189 if (m5Reg.submode != SixtyFourBitMode)
183 break;
184 case MISCREG_FIOFF:
185 case MISCREG_FOOFF:
186 if (m5Reg.submode != SixtyFourBitMode)
190 val &= (1ULL << 32) - 1;
187 reg_width = 32;
191 break;
192 default:
193 break;
194 }
195
188 break;
189 default:
190 break;
191 }
192
196 regVal[miscReg] = val;
193 regVal[miscReg] = val & mask(reg_width);
197}
198
199void
200ISA::setMiscReg(int miscReg, MiscReg val, ThreadContext * tc)
201{
202 MiscReg newVal = val;
203 switch(miscReg)
204 {

--- 226 unchanged lines hidden --- 		194}
195
196void
197ISA::setMiscReg(int miscReg, MiscReg val, ThreadContext * tc)
198{
199 MiscReg newVal = val;
200 switch(miscReg)
201 {

--- 226 unchanged lines hidden ---