isa.cc (10905:a6ca6831e775) isa.cc (11324:31ca646c7685)
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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124}
125
126MiscReg
127ISA::readMiscRegNoEffect(int miscReg) const
128{
129 // Make sure we're not dealing with an illegal control register.
130 // Instructions should filter out these indexes, and nothing else should
131 // attempt to read them directly.
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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124}
125
126MiscReg
127ISA::readMiscRegNoEffect(int miscReg) const
128{
129 // Make sure we're not dealing with an illegal control register.
130 // Instructions should filter out these indexes, and nothing else should
131 // attempt to read them directly.
132 assert(miscReg >= MISCREG_CR0 &&
133 miscReg < NUM_MISCREGS &&
134 miscReg != MISCREG_CR1 &&
135 !(miscReg > MISCREG_CR4 &&
136 miscReg < MISCREG_CR8) &&
137 !(miscReg > MISCREG_CR8 &&
138 miscReg <= MISCREG_CR15));
132 assert(isValidMiscReg(miscReg));
139
140 return regVal[miscReg];
141}
142
143MiscReg
144ISA::readMiscReg(int miscReg, ThreadContext * tc)
145{
146 if (miscReg == MISCREG_TSC) {

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157}
158
159void
160ISA::setMiscRegNoEffect(int miscReg, MiscReg val)
161{
162 // Make sure we're not dealing with an illegal control register.
163 // Instructions should filter out these indexes, and nothing else should
164 // attempt to write to them directly.
133
134 return regVal[miscReg];
135}
136
137MiscReg
138ISA::readMiscReg(int miscReg, ThreadContext * tc)
139{
140 if (miscReg == MISCREG_TSC) {

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151}
152
153void
154ISA::setMiscRegNoEffect(int miscReg, MiscReg val)
155{
156 // Make sure we're not dealing with an illegal control register.
157 // Instructions should filter out these indexes, and nothing else should
158 // attempt to write to them directly.
165 assert(miscReg >= MISCREG_CR0 &&
166 miscReg < NUM_MISCREGS &&
167 miscReg != MISCREG_CR1 &&
168 !(miscReg > MISCREG_CR4 &&
169 miscReg < MISCREG_CR8) &&
170 !(miscReg > MISCREG_CR8 &&
171 miscReg <= MISCREG_CR15));
159 assert(isValidMiscReg(miscReg));
172
173 HandyM5Reg m5Reg = readMiscRegNoEffect(MISCREG_M5_REG);
174 switch (miscReg) {
175 case MISCREG_FSW:
176 val &= (1ULL << 16) - 1;
177 regVal[miscReg] = val;
178 miscReg = MISCREG_X87_TOP;
179 val <<= 11;

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161 HandyM5Reg m5Reg = readMiscRegNoEffect(MISCREG_M5_REG);
162 switch (miscReg) {
163 case MISCREG_FSW:
164 val &= (1ULL << 16) - 1;
165 regVal[miscReg] = val;
166 miscReg = MISCREG_X87_TOP;
167 val <<= 11;

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