1/* 2 * Copyright (c) 2009 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 19 unchanged lines hidden (view full) --- 28 * Authors: Gabe Black 29 */ 30 31#include "arch/x86/decoder.hh" 32#include "arch/x86/isa.hh" 33#include "arch/x86/tlb.hh" 34#include "cpu/base.hh" 35#include "cpu/thread_context.hh" |
36#include "params/X86ISA.hh" |
37#include "sim/serialize.hh" 38 39namespace X86ISA 40{ 41 42void 43ISA::updateHandyM5Reg(Efer efer, CR0 cr0, 44 SegAttr csAttr, SegAttr ssAttr, RFLAGS rflags, --- 61 unchanged lines hidden (view full) --- 106{ 107 // Blank everything. 0 might not be an appropriate value for some things, 108 // but it is for most. 109 memset(regVal, 0, NumMiscRegs * sizeof(MiscReg)); 110 regVal[MISCREG_DR6] = (mask(8) << 4) | (mask(16) << 16); 111 regVal[MISCREG_DR7] = 1 << 10; 112} 113 |
114ISA::ISA(Params *p) 115 : SimObject(p) 116{ 117 clear(); 118} 119 120const X86ISAParams * 121ISA::params() const 122{ 123 return dynamic_cast<const Params *>(_params); 124} 125 |
126MiscReg 127ISA::readMiscRegNoEffect(int miscReg) 128{ 129 // Make sure we're not dealing with an illegal control register. 130 // Instructions should filter out these indexes, and nothing else should 131 // attempt to read them directly. 132 assert( miscReg != MISCREG_CR1 && 133 !(miscReg > MISCREG_CR4 && --- 250 unchanged lines hidden (view full) --- 384 regVal[MISCREG_CR0], 385 regVal[MISCREG_CS_ATTR], 386 regVal[MISCREG_SS_ATTR], 387 regVal[MISCREG_RFLAGS], 388 NULL); 389} 390 391} |
392 393X86ISA::ISA * 394X86ISAParams::create() 395{ 396 return new X86ISA::ISA(this); 397} |