148c148
< return (fsw & (~(7ULL << 11))) + (top << 11);
---
> return insertBits(fsw, 11, 13, top);
162c162,163
< HandyM5Reg m5Reg = readMiscRegNoEffect(MISCREG_M5_REG);
---
> HandyM5Reg m5Reg = regVal[MISCREG_M5_REG];
> int reg_width = 64;
164,168d164
< case MISCREG_FSW:
< val &= (1ULL << 16) - 1;
< regVal[miscReg] = val;
< miscReg = MISCREG_X87_TOP;
< val <<= 11;
170c166
< val &= (1ULL << 3) - 1;
---
> reg_width = 3;
173c169
< val &= (1ULL << 8) - 1;
---
> reg_width = 8;
174a171
> case MISCREG_FSW:
177c174
< val &= (1ULL << 16) - 1;
---
> reg_width = 16;
180c177
< val &= (1ULL << 32) - 1;
---
> reg_width = 32;
185c182
< val &= (1ULL << 16) - 1;
---
> reg_width = 16;
190c187
< val &= (1ULL << 32) - 1;
---
> reg_width = 32;
196c193
< regVal[miscReg] = val;
---
> regVal[miscReg] = val & mask(reg_width);