132,136c132,138
< assert( miscReg != MISCREG_CR1 &&
< !(miscReg > MISCREG_CR4 &&
< miscReg < MISCREG_CR8) &&
< !(miscReg > MISCREG_CR8 &&
< miscReg <= MISCREG_CR15));
---
> assert(miscReg >= MISCREG_CR0 &&
> miscReg < NUM_MISCREGS &&
> miscReg != MISCREG_CR1 &&
> !(miscReg > MISCREG_CR4 &&
> miscReg < MISCREG_CR8) &&
> !(miscReg > MISCREG_CR8 &&
> miscReg <= MISCREG_CR15));
163,167c165,206
< assert( miscReg != MISCREG_CR1 &&
< !(miscReg > MISCREG_CR4 &&
< miscReg < MISCREG_CR8) &&
< !(miscReg > MISCREG_CR8 &&
< miscReg <= MISCREG_CR15));
---
> assert(miscReg >= MISCREG_CR0 &&
> miscReg < NUM_MISCREGS &&
> miscReg != MISCREG_CR1 &&
> !(miscReg > MISCREG_CR4 &&
> miscReg < MISCREG_CR8) &&
> !(miscReg > MISCREG_CR8 &&
> miscReg <= MISCREG_CR15));
>
> HandyM5Reg m5Reg = readMiscRegNoEffect(MISCREG_M5_REG);
> switch (miscReg) {
> case MISCREG_FSW:
> val &= (1ULL << 16) - 1;
> regVal[miscReg] = val;
> miscReg = MISCREG_X87_TOP;
> val <<= 11;
> case MISCREG_X87_TOP:
> val &= (1ULL << 3) - 1;
> break;
> case MISCREG_FTW:
> val &= (1ULL << 8) - 1;
> break;
> case MISCREG_FCW:
> case MISCREG_FOP:
> val &= (1ULL << 16) - 1;
> break;
> case MISCREG_MXCSR:
> val &= (1ULL << 32) - 1;
> break;
> case MISCREG_FISEG:
> case MISCREG_FOSEG:
> if (m5Reg.submode != SixtyFourBitMode)
> val &= (1ULL << 16) - 1;
> break;
> case MISCREG_FIOFF:
> case MISCREG_FOOFF:
> if (m5Reg.submode != SixtyFourBitMode)
> val &= (1ULL << 32) - 1;
> break;
> default:
> break;
> }
>