isa.cc (6336:25635830e33c) | isa.cc (6359:1e4908b3e28e) |
---|---|
1/* 2 * Copyright (c) 2009 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Gabe Black 29 */ 30 | 1/* 2 * Copyright (c) 2009 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Gabe Black 29 */ 30 |
31#include "arch/x86/floatregs.hh" | |
32#include "arch/x86/isa.hh" 33#include "arch/x86/tlb.hh" 34#include "cpu/base.hh" 35#include "cpu/thread_context.hh" 36#include "sim/serialize.hh" 37 38namespace X86ISA 39{ 40 41void 42ISA::updateHandyM5Reg(Efer efer, CR0 cr0, 43 SegAttr csAttr, SegAttr ssAttr, RFLAGS rflags) 44{ 45 HandyM5Reg m5reg; 46 if (efer.lma) { 47 m5reg.mode = LongMode; 48 if (csAttr.longMode) 49 m5reg.submode = SixtyFourBitMode; 50 else 51 m5reg.submode = CompatabilityMode; 52 } else { 53 m5reg.mode = LegacyMode; 54 if (cr0.pe) { 55 if (rflags.vm) 56 m5reg.submode = Virtual8086Mode; 57 else 58 m5reg.submode = ProtectedMode; 59 } else { 60 m5reg.submode = RealMode; 61 } 62 } 63 m5reg.cpl = csAttr.dpl; 64 m5reg.paging = cr0.pg; 65 m5reg.prot = cr0.pe; 66 67 // Compute the default and alternate operand size. 68 if (m5reg.submode == SixtyFourBitMode || csAttr.defaultSize) { 69 m5reg.defOp = 2; 70 m5reg.altOp = 1; 71 } else { 72 m5reg.defOp = 1; 73 m5reg.altOp = 2; 74 } 75 76 // Compute the default and alternate address size. 77 if (m5reg.submode == SixtyFourBitMode) { 78 m5reg.defAddr = 3; 79 m5reg.altAddr = 2; 80 } else if (csAttr.defaultSize) { 81 m5reg.defAddr = 2; 82 m5reg.altAddr = 1; 83 } else { 84 m5reg.defAddr = 1; 85 m5reg.altAddr = 2; 86 } 87 88 // Compute the stack size 89 if (m5reg.submode == SixtyFourBitMode) { 90 m5reg.stack = 3; 91 } else if (ssAttr.defaultSize) { 92 m5reg.stack = 2; 93 } else { 94 m5reg.stack = 1; 95 } 96 97 regVal[MISCREG_M5_REG] = m5reg; 98} 99 100void 101ISA::clear() 102{ 103 // Blank everything. 0 might not be an appropriate value for some things, 104 // but it is for most. 105 memset(regVal, 0, NumMiscRegs * sizeof(MiscReg)); 106 regVal[MISCREG_DR6] = (mask(8) << 4) | (mask(16) << 16); 107 regVal[MISCREG_DR7] = 1 << 10; 108} 109 110MiscReg 111ISA::readMiscRegNoEffect(int miscReg) 112{ 113 // Make sure we're not dealing with an illegal control register. 114 // Instructions should filter out these indexes, and nothing else should 115 // attempt to read them directly. 116 assert( miscReg != MISCREG_CR1 && 117 !(miscReg > MISCREG_CR4 && 118 miscReg < MISCREG_CR8) && 119 !(miscReg > MISCREG_CR8 && 120 miscReg <= MISCREG_CR15)); 121 122 return regVal[miscReg]; 123} 124 125MiscReg 126ISA::readMiscReg(int miscReg, ThreadContext * tc) 127{ 128 if (miscReg == MISCREG_TSC) { 129 return regVal[MISCREG_TSC] + tc->getCpuPtr()->curCycle(); 130 } 131 return readMiscRegNoEffect(miscReg); 132} 133 134void 135ISA::setMiscRegNoEffect(int miscReg, MiscReg val) 136{ 137 // Make sure we're not dealing with an illegal control register. 138 // Instructions should filter out these indexes, and nothing else should 139 // attempt to write to them directly. 140 assert( miscReg != MISCREG_CR1 && 141 !(miscReg > MISCREG_CR4 && 142 miscReg < MISCREG_CR8) && 143 !(miscReg > MISCREG_CR8 && 144 miscReg <= MISCREG_CR15)); 145 regVal[miscReg] = val; 146} 147 148void 149ISA::setMiscReg(int miscReg, MiscReg val, ThreadContext * tc) 150{ 151 MiscReg newVal = val; 152 switch(miscReg) 153 { 154 case MISCREG_CR0: 155 { 156 CR0 toggled = regVal[miscReg] ^ val; 157 CR0 newCR0 = val; 158 Efer efer = regVal[MISCREG_EFER]; 159 if (toggled.pg && efer.lme) { 160 if (newCR0.pg) { 161 //Turning on long mode 162 efer.lma = 1; 163 regVal[MISCREG_EFER] = efer; 164 } else { 165 //Turning off long mode 166 efer.lma = 0; 167 regVal[MISCREG_EFER] = efer; 168 } 169 } 170 if (toggled.pg) { 171 tc->getITBPtr()->invalidateAll(); 172 tc->getDTBPtr()->invalidateAll(); 173 } 174 //This must always be 1. 175 newCR0.et = 1; 176 newVal = newCR0; 177 updateHandyM5Reg(regVal[MISCREG_EFER], 178 newCR0, 179 regVal[MISCREG_CS_ATTR], 180 regVal[MISCREG_SS_ATTR], 181 regVal[MISCREG_RFLAGS]); 182 } 183 break; 184 case MISCREG_CR2: 185 break; 186 case MISCREG_CR3: 187 tc->getITBPtr()->invalidateNonGlobal(); 188 tc->getDTBPtr()->invalidateNonGlobal(); 189 break; 190 case MISCREG_CR4: 191 { 192 CR4 toggled = regVal[miscReg] ^ val; 193 if (toggled.pae || toggled.pse || toggled.pge) { 194 tc->getITBPtr()->invalidateAll(); 195 tc->getDTBPtr()->invalidateAll(); 196 } 197 } 198 break; 199 case MISCREG_CR8: 200 break; 201 case MISCREG_CS_ATTR: 202 { 203 SegAttr toggled = regVal[miscReg] ^ val; 204 SegAttr newCSAttr = val; 205 if (toggled.longMode) { 206 if (newCSAttr.longMode) { 207 regVal[MISCREG_ES_EFF_BASE] = 0; 208 regVal[MISCREG_CS_EFF_BASE] = 0; 209 regVal[MISCREG_SS_EFF_BASE] = 0; 210 regVal[MISCREG_DS_EFF_BASE] = 0; 211 } else { 212 regVal[MISCREG_ES_EFF_BASE] = regVal[MISCREG_ES_BASE]; 213 regVal[MISCREG_CS_EFF_BASE] = regVal[MISCREG_CS_BASE]; 214 regVal[MISCREG_SS_EFF_BASE] = regVal[MISCREG_SS_BASE]; 215 regVal[MISCREG_DS_EFF_BASE] = regVal[MISCREG_DS_BASE]; 216 } 217 } 218 updateHandyM5Reg(regVal[MISCREG_EFER], 219 regVal[MISCREG_CR0], 220 newCSAttr, 221 regVal[MISCREG_SS_ATTR], 222 regVal[MISCREG_RFLAGS]); 223 } 224 break; 225 case MISCREG_SS_ATTR: 226 updateHandyM5Reg(regVal[MISCREG_EFER], 227 regVal[MISCREG_CR0], 228 regVal[MISCREG_CS_ATTR], 229 val, 230 regVal[MISCREG_RFLAGS]); 231 break; 232 // These segments always actually use their bases, or in other words 233 // their effective bases must stay equal to their actual bases. 234 case MISCREG_FS_BASE: 235 case MISCREG_GS_BASE: 236 case MISCREG_HS_BASE: 237 case MISCREG_TSL_BASE: 238 case MISCREG_TSG_BASE: 239 case MISCREG_TR_BASE: 240 case MISCREG_IDTR_BASE: 241 regVal[MISCREG_SEG_EFF_BASE(miscReg - MISCREG_SEG_BASE_BASE)] = val; 242 break; 243 // These segments ignore their bases in 64 bit mode. 244 // their effective bases must stay equal to their actual bases. 245 case MISCREG_ES_BASE: 246 case MISCREG_CS_BASE: 247 case MISCREG_SS_BASE: 248 case MISCREG_DS_BASE: 249 { 250 Efer efer = regVal[MISCREG_EFER]; 251 SegAttr csAttr = regVal[MISCREG_CS_ATTR]; 252 if (!efer.lma || !csAttr.longMode) // Check for non 64 bit mode. 253 regVal[MISCREG_SEG_EFF_BASE(miscReg - 254 MISCREG_SEG_BASE_BASE)] = val; 255 } 256 break; 257 case MISCREG_TSC: 258 regVal[MISCREG_TSC] = val - tc->getCpuPtr()->curCycle(); 259 return; 260 case MISCREG_DR0: 261 case MISCREG_DR1: 262 case MISCREG_DR2: 263 case MISCREG_DR3: 264 /* These should eventually set up breakpoints. */ 265 break; 266 case MISCREG_DR4: 267 miscReg = MISCREG_DR6; 268 /* Fall through to have the same effects as DR6. */ 269 case MISCREG_DR6: 270 { 271 DR6 dr6 = regVal[MISCREG_DR6]; 272 DR6 newDR6 = val; 273 dr6.b0 = newDR6.b0; 274 dr6.b1 = newDR6.b1; 275 dr6.b2 = newDR6.b2; 276 dr6.b3 = newDR6.b3; 277 dr6.bd = newDR6.bd; 278 dr6.bs = newDR6.bs; 279 dr6.bt = newDR6.bt; 280 newVal = dr6; 281 } 282 break; 283 case MISCREG_DR5: 284 miscReg = MISCREG_DR7; 285 /* Fall through to have the same effects as DR7. */ 286 case MISCREG_DR7: 287 { 288 DR7 dr7 = regVal[MISCREG_DR7]; 289 DR7 newDR7 = val; 290 dr7.l0 = newDR7.l0; 291 dr7.g0 = newDR7.g0; 292 if (dr7.l0 || dr7.g0) { 293 panic("Debug register breakpoints not implemented.\n"); 294 } else { 295 /* Disable breakpoint 0. */ 296 } 297 dr7.l1 = newDR7.l1; 298 dr7.g1 = newDR7.g1; 299 if (dr7.l1 || dr7.g1) { 300 panic("Debug register breakpoints not implemented.\n"); 301 } else { 302 /* Disable breakpoint 1. */ 303 } 304 dr7.l2 = newDR7.l2; 305 dr7.g2 = newDR7.g2; 306 if (dr7.l2 || dr7.g2) { 307 panic("Debug register breakpoints not implemented.\n"); 308 } else { 309 /* Disable breakpoint 2. */ 310 } 311 dr7.l3 = newDR7.l3; 312 dr7.g3 = newDR7.g3; 313 if (dr7.l3 || dr7.g3) { 314 panic("Debug register breakpoints not implemented.\n"); 315 } else { 316 /* Disable breakpoint 3. */ 317 } 318 dr7.gd = newDR7.gd; 319 dr7.rw0 = newDR7.rw0; 320 dr7.len0 = newDR7.len0; 321 dr7.rw1 = newDR7.rw1; 322 dr7.len1 = newDR7.len1; 323 dr7.rw2 = newDR7.rw2; 324 dr7.len2 = newDR7.len2; 325 dr7.rw3 = newDR7.rw3; 326 dr7.len3 = newDR7.len3; 327 } 328 break; 329 case MISCREG_M5_REG: 330 // Writing anything to the m5reg with side effects makes it update 331 // based on the current values of the relevant registers. The actual 332 // value written is discarded. 333 updateHandyM5Reg(regVal[MISCREG_EFER], 334 regVal[MISCREG_CR0], 335 regVal[MISCREG_CS_ATTR], 336 regVal[MISCREG_SS_ATTR], 337 regVal[MISCREG_RFLAGS]); 338 return; 339 default: 340 break; 341 } 342 setMiscRegNoEffect(miscReg, newVal); 343} 344 345void 346ISA::serialize(EventManager *em, std::ostream & os) 347{ 348 SERIALIZE_ARRAY(regVal, NumMiscRegs); 349} 350 351void 352ISA::unserialize(EventManager *em, Checkpoint * cp, 353 const std::string & section) 354{ 355 UNSERIALIZE_ARRAY(regVal, NumMiscRegs); 356} 357 | 31#include "arch/x86/isa.hh" 32#include "arch/x86/tlb.hh" 33#include "cpu/base.hh" 34#include "cpu/thread_context.hh" 35#include "sim/serialize.hh" 36 37namespace X86ISA 38{ 39 40void 41ISA::updateHandyM5Reg(Efer efer, CR0 cr0, 42 SegAttr csAttr, SegAttr ssAttr, RFLAGS rflags) 43{ 44 HandyM5Reg m5reg; 45 if (efer.lma) { 46 m5reg.mode = LongMode; 47 if (csAttr.longMode) 48 m5reg.submode = SixtyFourBitMode; 49 else 50 m5reg.submode = CompatabilityMode; 51 } else { 52 m5reg.mode = LegacyMode; 53 if (cr0.pe) { 54 if (rflags.vm) 55 m5reg.submode = Virtual8086Mode; 56 else 57 m5reg.submode = ProtectedMode; 58 } else { 59 m5reg.submode = RealMode; 60 } 61 } 62 m5reg.cpl = csAttr.dpl; 63 m5reg.paging = cr0.pg; 64 m5reg.prot = cr0.pe; 65 66 // Compute the default and alternate operand size. 67 if (m5reg.submode == SixtyFourBitMode || csAttr.defaultSize) { 68 m5reg.defOp = 2; 69 m5reg.altOp = 1; 70 } else { 71 m5reg.defOp = 1; 72 m5reg.altOp = 2; 73 } 74 75 // Compute the default and alternate address size. 76 if (m5reg.submode == SixtyFourBitMode) { 77 m5reg.defAddr = 3; 78 m5reg.altAddr = 2; 79 } else if (csAttr.defaultSize) { 80 m5reg.defAddr = 2; 81 m5reg.altAddr = 1; 82 } else { 83 m5reg.defAddr = 1; 84 m5reg.altAddr = 2; 85 } 86 87 // Compute the stack size 88 if (m5reg.submode == SixtyFourBitMode) { 89 m5reg.stack = 3; 90 } else if (ssAttr.defaultSize) { 91 m5reg.stack = 2; 92 } else { 93 m5reg.stack = 1; 94 } 95 96 regVal[MISCREG_M5_REG] = m5reg; 97} 98 99void 100ISA::clear() 101{ 102 // Blank everything. 0 might not be an appropriate value for some things, 103 // but it is for most. 104 memset(regVal, 0, NumMiscRegs * sizeof(MiscReg)); 105 regVal[MISCREG_DR6] = (mask(8) << 4) | (mask(16) << 16); 106 regVal[MISCREG_DR7] = 1 << 10; 107} 108 109MiscReg 110ISA::readMiscRegNoEffect(int miscReg) 111{ 112 // Make sure we're not dealing with an illegal control register. 113 // Instructions should filter out these indexes, and nothing else should 114 // attempt to read them directly. 115 assert( miscReg != MISCREG_CR1 && 116 !(miscReg > MISCREG_CR4 && 117 miscReg < MISCREG_CR8) && 118 !(miscReg > MISCREG_CR8 && 119 miscReg <= MISCREG_CR15)); 120 121 return regVal[miscReg]; 122} 123 124MiscReg 125ISA::readMiscReg(int miscReg, ThreadContext * tc) 126{ 127 if (miscReg == MISCREG_TSC) { 128 return regVal[MISCREG_TSC] + tc->getCpuPtr()->curCycle(); 129 } 130 return readMiscRegNoEffect(miscReg); 131} 132 133void 134ISA::setMiscRegNoEffect(int miscReg, MiscReg val) 135{ 136 // Make sure we're not dealing with an illegal control register. 137 // Instructions should filter out these indexes, and nothing else should 138 // attempt to write to them directly. 139 assert( miscReg != MISCREG_CR1 && 140 !(miscReg > MISCREG_CR4 && 141 miscReg < MISCREG_CR8) && 142 !(miscReg > MISCREG_CR8 && 143 miscReg <= MISCREG_CR15)); 144 regVal[miscReg] = val; 145} 146 147void 148ISA::setMiscReg(int miscReg, MiscReg val, ThreadContext * tc) 149{ 150 MiscReg newVal = val; 151 switch(miscReg) 152 { 153 case MISCREG_CR0: 154 { 155 CR0 toggled = regVal[miscReg] ^ val; 156 CR0 newCR0 = val; 157 Efer efer = regVal[MISCREG_EFER]; 158 if (toggled.pg && efer.lme) { 159 if (newCR0.pg) { 160 //Turning on long mode 161 efer.lma = 1; 162 regVal[MISCREG_EFER] = efer; 163 } else { 164 //Turning off long mode 165 efer.lma = 0; 166 regVal[MISCREG_EFER] = efer; 167 } 168 } 169 if (toggled.pg) { 170 tc->getITBPtr()->invalidateAll(); 171 tc->getDTBPtr()->invalidateAll(); 172 } 173 //This must always be 1. 174 newCR0.et = 1; 175 newVal = newCR0; 176 updateHandyM5Reg(regVal[MISCREG_EFER], 177 newCR0, 178 regVal[MISCREG_CS_ATTR], 179 regVal[MISCREG_SS_ATTR], 180 regVal[MISCREG_RFLAGS]); 181 } 182 break; 183 case MISCREG_CR2: 184 break; 185 case MISCREG_CR3: 186 tc->getITBPtr()->invalidateNonGlobal(); 187 tc->getDTBPtr()->invalidateNonGlobal(); 188 break; 189 case MISCREG_CR4: 190 { 191 CR4 toggled = regVal[miscReg] ^ val; 192 if (toggled.pae || toggled.pse || toggled.pge) { 193 tc->getITBPtr()->invalidateAll(); 194 tc->getDTBPtr()->invalidateAll(); 195 } 196 } 197 break; 198 case MISCREG_CR8: 199 break; 200 case MISCREG_CS_ATTR: 201 { 202 SegAttr toggled = regVal[miscReg] ^ val; 203 SegAttr newCSAttr = val; 204 if (toggled.longMode) { 205 if (newCSAttr.longMode) { 206 regVal[MISCREG_ES_EFF_BASE] = 0; 207 regVal[MISCREG_CS_EFF_BASE] = 0; 208 regVal[MISCREG_SS_EFF_BASE] = 0; 209 regVal[MISCREG_DS_EFF_BASE] = 0; 210 } else { 211 regVal[MISCREG_ES_EFF_BASE] = regVal[MISCREG_ES_BASE]; 212 regVal[MISCREG_CS_EFF_BASE] = regVal[MISCREG_CS_BASE]; 213 regVal[MISCREG_SS_EFF_BASE] = regVal[MISCREG_SS_BASE]; 214 regVal[MISCREG_DS_EFF_BASE] = regVal[MISCREG_DS_BASE]; 215 } 216 } 217 updateHandyM5Reg(regVal[MISCREG_EFER], 218 regVal[MISCREG_CR0], 219 newCSAttr, 220 regVal[MISCREG_SS_ATTR], 221 regVal[MISCREG_RFLAGS]); 222 } 223 break; 224 case MISCREG_SS_ATTR: 225 updateHandyM5Reg(regVal[MISCREG_EFER], 226 regVal[MISCREG_CR0], 227 regVal[MISCREG_CS_ATTR], 228 val, 229 regVal[MISCREG_RFLAGS]); 230 break; 231 // These segments always actually use their bases, or in other words 232 // their effective bases must stay equal to their actual bases. 233 case MISCREG_FS_BASE: 234 case MISCREG_GS_BASE: 235 case MISCREG_HS_BASE: 236 case MISCREG_TSL_BASE: 237 case MISCREG_TSG_BASE: 238 case MISCREG_TR_BASE: 239 case MISCREG_IDTR_BASE: 240 regVal[MISCREG_SEG_EFF_BASE(miscReg - MISCREG_SEG_BASE_BASE)] = val; 241 break; 242 // These segments ignore their bases in 64 bit mode. 243 // their effective bases must stay equal to their actual bases. 244 case MISCREG_ES_BASE: 245 case MISCREG_CS_BASE: 246 case MISCREG_SS_BASE: 247 case MISCREG_DS_BASE: 248 { 249 Efer efer = regVal[MISCREG_EFER]; 250 SegAttr csAttr = regVal[MISCREG_CS_ATTR]; 251 if (!efer.lma || !csAttr.longMode) // Check for non 64 bit mode. 252 regVal[MISCREG_SEG_EFF_BASE(miscReg - 253 MISCREG_SEG_BASE_BASE)] = val; 254 } 255 break; 256 case MISCREG_TSC: 257 regVal[MISCREG_TSC] = val - tc->getCpuPtr()->curCycle(); 258 return; 259 case MISCREG_DR0: 260 case MISCREG_DR1: 261 case MISCREG_DR2: 262 case MISCREG_DR3: 263 /* These should eventually set up breakpoints. */ 264 break; 265 case MISCREG_DR4: 266 miscReg = MISCREG_DR6; 267 /* Fall through to have the same effects as DR6. */ 268 case MISCREG_DR6: 269 { 270 DR6 dr6 = regVal[MISCREG_DR6]; 271 DR6 newDR6 = val; 272 dr6.b0 = newDR6.b0; 273 dr6.b1 = newDR6.b1; 274 dr6.b2 = newDR6.b2; 275 dr6.b3 = newDR6.b3; 276 dr6.bd = newDR6.bd; 277 dr6.bs = newDR6.bs; 278 dr6.bt = newDR6.bt; 279 newVal = dr6; 280 } 281 break; 282 case MISCREG_DR5: 283 miscReg = MISCREG_DR7; 284 /* Fall through to have the same effects as DR7. */ 285 case MISCREG_DR7: 286 { 287 DR7 dr7 = regVal[MISCREG_DR7]; 288 DR7 newDR7 = val; 289 dr7.l0 = newDR7.l0; 290 dr7.g0 = newDR7.g0; 291 if (dr7.l0 || dr7.g0) { 292 panic("Debug register breakpoints not implemented.\n"); 293 } else { 294 /* Disable breakpoint 0. */ 295 } 296 dr7.l1 = newDR7.l1; 297 dr7.g1 = newDR7.g1; 298 if (dr7.l1 || dr7.g1) { 299 panic("Debug register breakpoints not implemented.\n"); 300 } else { 301 /* Disable breakpoint 1. */ 302 } 303 dr7.l2 = newDR7.l2; 304 dr7.g2 = newDR7.g2; 305 if (dr7.l2 || dr7.g2) { 306 panic("Debug register breakpoints not implemented.\n"); 307 } else { 308 /* Disable breakpoint 2. */ 309 } 310 dr7.l3 = newDR7.l3; 311 dr7.g3 = newDR7.g3; 312 if (dr7.l3 || dr7.g3) { 313 panic("Debug register breakpoints not implemented.\n"); 314 } else { 315 /* Disable breakpoint 3. */ 316 } 317 dr7.gd = newDR7.gd; 318 dr7.rw0 = newDR7.rw0; 319 dr7.len0 = newDR7.len0; 320 dr7.rw1 = newDR7.rw1; 321 dr7.len1 = newDR7.len1; 322 dr7.rw2 = newDR7.rw2; 323 dr7.len2 = newDR7.len2; 324 dr7.rw3 = newDR7.rw3; 325 dr7.len3 = newDR7.len3; 326 } 327 break; 328 case MISCREG_M5_REG: 329 // Writing anything to the m5reg with side effects makes it update 330 // based on the current values of the relevant registers. The actual 331 // value written is discarded. 332 updateHandyM5Reg(regVal[MISCREG_EFER], 333 regVal[MISCREG_CR0], 334 regVal[MISCREG_CS_ATTR], 335 regVal[MISCREG_SS_ATTR], 336 regVal[MISCREG_RFLAGS]); 337 return; 338 default: 339 break; 340 } 341 setMiscRegNoEffect(miscReg, newVal); 342} 343 344void 345ISA::serialize(EventManager *em, std::ostream & os) 346{ 347 SERIALIZE_ARRAY(regVal, NumMiscRegs); 348} 349 350void 351ISA::unserialize(EventManager *em, Checkpoint * cp, 352 const std::string & section) 353{ 354 UNSERIALIZE_ARRAY(regVal, NumMiscRegs); 355} 356 |
358int 359ISA::flattenIntIndex(int reg) 360{ 361 //If we need to fold over the index to match byte semantics, do that. 362 //Otherwise, just strip off any extra bits and pass it through. 363 if (reg & (1 << 6)) 364 return (reg & (~(1 << 6) - 0x4)); 365 else 366 return (reg & ~(1 << 6)); | |
367} | 357} |
368 369int 370ISA::flattenFloatIndex(int reg) 371{ 372 if (reg >= NUM_FLOATREGS) { 373 int top = readMiscRegNoEffect(MISCREG_X87_TOP); 374 reg = FLOATREG_STACK(reg - NUM_FLOATREGS, top); 375 } 376 return reg; 377} 378 379} | |