isa.cc (10698:829adc48e175) | isa.cc (10899:b8b8ad2c72dd) |
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1/* 2 * Copyright (c) 2009 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 115 unchanged lines hidden (view full) --- 124} 125 126MiscReg 127ISA::readMiscRegNoEffect(int miscReg) const 128{ 129 // Make sure we're not dealing with an illegal control register. 130 // Instructions should filter out these indexes, and nothing else should 131 // attempt to read them directly. | 1/* 2 * Copyright (c) 2009 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 115 unchanged lines hidden (view full) --- 124} 125 126MiscReg 127ISA::readMiscRegNoEffect(int miscReg) const 128{ 129 // Make sure we're not dealing with an illegal control register. 130 // Instructions should filter out these indexes, and nothing else should 131 // attempt to read them directly. |
132 assert( miscReg != MISCREG_CR1 && 133 !(miscReg > MISCREG_CR4 && 134 miscReg < MISCREG_CR8) && 135 !(miscReg > MISCREG_CR8 && 136 miscReg <= MISCREG_CR15)); | 132 assert(miscReg >= MISCREG_CR0 && 133 miscReg < NUM_MISCREGS && 134 miscReg != MISCREG_CR1 && 135 !(miscReg > MISCREG_CR4 && 136 miscReg < MISCREG_CR8) && 137 !(miscReg > MISCREG_CR8 && 138 miscReg <= MISCREG_CR15)); |
137 138 return regVal[miscReg]; 139} 140 141MiscReg 142ISA::readMiscReg(int miscReg, ThreadContext * tc) 143{ 144 if (miscReg == MISCREG_TSC) { --- 10 unchanged lines hidden (view full) --- 155} 156 157void 158ISA::setMiscRegNoEffect(int miscReg, MiscReg val) 159{ 160 // Make sure we're not dealing with an illegal control register. 161 // Instructions should filter out these indexes, and nothing else should 162 // attempt to write to them directly. | 139 140 return regVal[miscReg]; 141} 142 143MiscReg 144ISA::readMiscReg(int miscReg, ThreadContext * tc) 145{ 146 if (miscReg == MISCREG_TSC) { --- 10 unchanged lines hidden (view full) --- 157} 158 159void 160ISA::setMiscRegNoEffect(int miscReg, MiscReg val) 161{ 162 // Make sure we're not dealing with an illegal control register. 163 // Instructions should filter out these indexes, and nothing else should 164 // attempt to write to them directly. |
163 assert( miscReg != MISCREG_CR1 && 164 !(miscReg > MISCREG_CR4 && 165 miscReg < MISCREG_CR8) && 166 !(miscReg > MISCREG_CR8 && 167 miscReg <= MISCREG_CR15)); | 165 assert(miscReg >= MISCREG_CR0 && 166 miscReg < NUM_MISCREGS && 167 miscReg != MISCREG_CR1 && 168 !(miscReg > MISCREG_CR4 && 169 miscReg < MISCREG_CR8) && 170 !(miscReg > MISCREG_CR8 && 171 miscReg <= MISCREG_CR15)); 172 173 HandyM5Reg m5Reg = readMiscRegNoEffect(MISCREG_M5_REG); 174 switch (miscReg) { 175 case MISCREG_FSW: 176 val &= (1ULL << 16) - 1; 177 regVal[miscReg] = val; 178 miscReg = MISCREG_X87_TOP; 179 val <<= 11; 180 case MISCREG_X87_TOP: 181 val &= (1ULL << 3) - 1; 182 break; 183 case MISCREG_FTW: 184 val &= (1ULL << 8) - 1; 185 break; 186 case MISCREG_FCW: 187 case MISCREG_FOP: 188 val &= (1ULL << 16) - 1; 189 break; 190 case MISCREG_MXCSR: 191 val &= (1ULL << 32) - 1; 192 break; 193 case MISCREG_FISEG: 194 case MISCREG_FOSEG: 195 if (m5Reg.submode != SixtyFourBitMode) 196 val &= (1ULL << 16) - 1; 197 break; 198 case MISCREG_FIOFF: 199 case MISCREG_FOOFF: 200 if (m5Reg.submode != SixtyFourBitMode) 201 val &= (1ULL << 32) - 1; 202 break; 203 default: 204 break; 205 } 206 |
168 regVal[miscReg] = val; 169} 170 171void 172ISA::setMiscReg(int miscReg, MiscReg val, ThreadContext * tc) 173{ 174 MiscReg newVal = val; 175 switch(miscReg) --- 227 unchanged lines hidden --- | 207 regVal[miscReg] = val; 208} 209 210void 211ISA::setMiscReg(int miscReg, MiscReg val, ThreadContext * tc) 212{ 213 MiscReg newVal = val; 214 switch(miscReg) --- 227 unchanged lines hidden --- |