1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 115 unchanged lines hidden (view full) ---

124}
125
126MiscReg
127ISA::readMiscRegNoEffect(int miscReg) const
128{
129 // Make sure we're not dealing with an illegal control register.
130 // Instructions should filter out these indexes, and nothing else should
131 // attempt to read them directly.
132 assert( miscReg != MISCREG_CR1 &&
133 !(miscReg > MISCREG_CR4 &&
134 miscReg < MISCREG_CR8) &&
135 !(miscReg > MISCREG_CR8 &&
136 miscReg <= MISCREG_CR15));
137
138 return regVal[miscReg];
139}
140
141MiscReg
142ISA::readMiscReg(int miscReg, ThreadContext * tc)
143{
144 if (miscReg == MISCREG_TSC) {

--- 10 unchanged lines hidden (view full) ---

155}
156
157void
158ISA::setMiscRegNoEffect(int miscReg, MiscReg val)
159{
160 // Make sure we're not dealing with an illegal control register.
161 // Instructions should filter out these indexes, and nothing else should
162 // attempt to write to them directly.
163 assert( miscReg != MISCREG_CR1 &&
164 !(miscReg > MISCREG_CR4 &&
165 miscReg < MISCREG_CR8) &&
166 !(miscReg > MISCREG_CR8 &&
167 miscReg <= MISCREG_CR15));
168 regVal[miscReg] = val;
169}
170
171void
172ISA::setMiscReg(int miscReg, MiscReg val, ThreadContext * tc)
173{
174 MiscReg newVal = val;
175 switch(miscReg)

--- 227 unchanged lines hidden ---