interrupts.hh (9544:1a075d9bc1bc) interrupts.hh (9554:406fbcf60223)
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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61#include "dev/x86/intdev.hh"
62#include "dev/io_device.hh"
63#include "params/X86LocalApic.hh"
64#include "sim/eventq.hh"
65
66class ThreadContext;
67class BaseCPU;
68
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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61#include "dev/x86/intdev.hh"
62#include "dev/io_device.hh"
63#include "params/X86LocalApic.hh"
64#include "sim/eventq.hh"
65
66class ThreadContext;
67class BaseCPU;
68
69int divideFromConf(uint32_t conf);
70
69namespace X86ISA {
70
71namespace X86ISA {
72
73ApicRegIndex decodeAddr(Addr paddr);
74
71class Interrupts : public BasicPioDevice, IntDev
72{
73 protected:
74 // Storage for the APIC registers
75 uint32_t regs[NUM_APIC_REGS];
76
77 BitUnion32(LVTEntry)
78 Bitfield<7, 0> vector;

--- 233 unchanged lines hidden --- 		75class Interrupts : public BasicPioDevice, IntDev
76{
77 protected:
78 // Storage for the APIC registers
79 uint32_t regs[NUM_APIC_REGS];
80
81 BitUnion32(LVTEntry)
82 Bitfield<7, 0> vector;

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