interrupts.hh (5691:28d6ff8b94e2) | interrupts.hh (5704:98224505352a) |
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1/* 2 * Copyright (c) 2007 The Hewlett-Packard Development Company 3 * All rights reserved. 4 * 5 * Redistribution and use of this software in source and binary forms, 6 * with or without modification, are permitted provided that the 7 * following conditions are met: 8 * --- 56 unchanged lines hidden (view full) --- 65#include "cpu/thread_context.hh" 66#include "dev/io_device.hh" 67#include "dev/x86/intdev.hh" 68#include "params/X86LocalApic.hh" 69#include "sim/eventq.hh" 70 71class ThreadContext; 72 | 1/* 2 * Copyright (c) 2007 The Hewlett-Packard Development Company 3 * All rights reserved. 4 * 5 * Redistribution and use of this software in source and binary forms, 6 * with or without modification, are permitted provided that the 7 * following conditions are met: 8 * --- 56 unchanged lines hidden (view full) --- 65#include "cpu/thread_context.hh" 66#include "dev/io_device.hh" 67#include "dev/x86/intdev.hh" 68#include "params/X86LocalApic.hh" 69#include "sim/eventq.hh" 70 71class ThreadContext; 72 |
73namespace X86ISA 74{ | 73namespace X86ISA { |
75 76class Interrupts : public BasicPioDevice, IntDev 77{ 78 protected: 79 // Storage for the APIC registers 80 uint32_t regs[NUM_APIC_REGS]; 81 82 BitUnion32(LVTEntry) --- 101 unchanged lines hidden (view full) --- 184 void requestInterrupt(uint8_t vector, uint8_t deliveryMode, bool level); 185 186 public: 187 /* 188 * Params stuff. 189 */ 190 typedef X86LocalApicParams Params; 191 | 74 75class Interrupts : public BasicPioDevice, IntDev 76{ 77 protected: 78 // Storage for the APIC registers 79 uint32_t regs[NUM_APIC_REGS]; 80 81 BitUnion32(LVTEntry) --- 101 unchanged lines hidden (view full) --- 183 void requestInterrupt(uint8_t vector, uint8_t deliveryMode, bool level); 184 185 public: 186 /* 187 * Params stuff. 188 */ 189 typedef X86LocalApicParams Params; 190 |
192 void setClock(Tick newClock) | 191 void 192 setClock(Tick newClock) |
193 { 194 clock = newClock; 195 } 196 197 const Params * 198 params() const 199 { 200 return dynamic_cast<const Params *>(_params); --- 37 unchanged lines hidden (view full) --- 238 } 239 240 /* 241 * Functions to access and manipulate the APIC's registers. 242 */ 243 244 uint32_t readReg(ApicRegIndex miscReg); 245 void setReg(ApicRegIndex reg, uint32_t val); | 193 { 194 clock = newClock; 195 } 196 197 const Params * 198 params() const 199 { 200 return dynamic_cast<const Params *>(_params); --- 37 unchanged lines hidden (view full) --- 238 } 239 240 /* 241 * Functions to access and manipulate the APIC's registers. 242 */ 243 244 uint32_t readReg(ApicRegIndex miscReg); 245 void setReg(ApicRegIndex reg, uint32_t val); |
246 void setRegNoEffect(ApicRegIndex reg, uint32_t val) | 246 void 247 setRegNoEffect(ApicRegIndex reg, uint32_t val) |
247 { 248 regs[reg] = val; 249 } 250 251 /* 252 * Constructor. 253 */ 254 | 248 { 249 regs[reg] = val; 250 } 251 252 /* 253 * Constructor. 254 */ 255 |
255 Interrupts(Params * p) : BasicPioDevice(p), IntDev(this), 256 latency(p->pio_latency), clock(0), 257 apicTimerEvent(this), 258 pendingSmi(false), smiVector(0), 259 pendingNmi(false), nmiVector(0), 260 pendingExtInt(false), extIntVector(0), 261 pendingInit(false), initVector(0), 262 pendingUnmaskableInt(false) | 256 Interrupts(Params * p) 257 : BasicPioDevice(p), IntDev(this), latency(p->pio_latency), clock(0), 258 apicTimerEvent(this), 259 pendingSmi(false), smiVector(0), 260 pendingNmi(false), nmiVector(0), 261 pendingExtInt(false), extIntVector(0), 262 pendingInit(false), initVector(0), 263 pendingUnmaskableInt(false) |
263 { 264 pioSize = PageBytes; 265 memset(regs, 0, sizeof(regs)); 266 //Set the local apic DFR to the flat model. 267 regs[APIC_DESTINATION_FORMAT] = (uint32_t)(-1); 268 ISRV = 0; 269 IRRV = 0; 270 } 271 272 /* 273 * Functions for retrieving interrupts for the CPU to handle. 274 */ 275 | 264 { 265 pioSize = PageBytes; 266 memset(regs, 0, sizeof(regs)); 267 //Set the local apic DFR to the flat model. 268 regs[APIC_DESTINATION_FORMAT] = (uint32_t)(-1); 269 ISRV = 0; 270 IRRV = 0; 271 } 272 273 /* 274 * Functions for retrieving interrupts for the CPU to handle. 275 */ 276 |
276 bool check_interrupts(ThreadContext * tc) const; 277 Fault getInterrupt(ThreadContext * tc); 278 void updateIntrInfo(ThreadContext * tc); | 277 bool checkInterrupts(ThreadContext *tc) const; 278 Fault getInterrupt(ThreadContext *tc); 279 void updateIntrInfo(ThreadContext *tc); |
279 280 /* 281 * Serialization. 282 */ 283 | 280 281 /* 282 * Serialization. 283 */ 284 |
284 void serialize(std::ostream & os) | 285 void 286 serialize(std::ostream &os) |
285 { 286 panic("Interrupts::serialize unimplemented!\n"); 287 } 288 | 287 { 288 panic("Interrupts::serialize unimplemented!\n"); 289 } 290 |
289 void unserialize(Checkpoint * cp, const std::string & section) | 291 void 292 unserialize(Checkpoint *cp, const std::string §ion) |
290 { 291 panic("Interrupts::unserialize unimplemented!\n"); 292 } 293 294 /* 295 * Old functions needed for compatability but which will be phased out 296 * eventually. 297 */ | 293 { 294 panic("Interrupts::unserialize unimplemented!\n"); 295 } 296 297 /* 298 * Old functions needed for compatability but which will be phased out 299 * eventually. 300 */ |
298 void post(int int_num, int index) | 301 void 302 post(int int_num, int index) |
299 { 300 panic("Interrupts::post unimplemented!\n"); 301 } 302 | 303 { 304 panic("Interrupts::post unimplemented!\n"); 305 } 306 |
303 void clear(int int_num, int index) | 307 void 308 clear(int int_num, int index) |
304 { 305 panic("Interrupts::clear unimplemented!\n"); 306 } 307 | 309 { 310 panic("Interrupts::clear unimplemented!\n"); 311 } 312 |
308 void clear_all() | 313 void 314 clearAll() |
309 { | 315 { |
310 panic("Interrupts::clear_all unimplemented!\n"); | 316 panic("Interrupts::clearAll unimplemented!\n"); |
311 } 312}; 313 | 317 } 318}; 319 |
314}; | 320} // namespace X86ISA |
315 316#endif // __ARCH_X86_INTERRUPTS_HH__ | 321 322#endif // __ARCH_X86_INTERRUPTS_HH__ |